Manual

CS5490
DS982F3 39
6.6.12 Interrupt Status (Status0) – Page 0, Address 23
Default = 0x 00 0000
The Status0 register indicates a variety of conditions within the chip.
Writing a one to a Status0 register bit will clear that bit. Writing a zero to any bit has no effect.
DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated.
It indicates completion of other host instruction and the reset sequence.
CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updat-
ed.
WOF Watchdog timer overflow.
[20:19] Reserved.
MIPS MIPS overflow.
Sets when the calculation engine has not completed processing a sample before the next
one arrives.
[17] Reserved.
VSWELL Voltage channel swell event detected.
[15] Reserved.
POR Power out of range. Sets when the measured power would cause the P register to overflow.
[13] Reserved.
IOR Current out of range. Set when the measured current would cause the I register to overflow.
[11] Reserved.
VOR Voltage out of range. Set when the measured voltage would cause the V register to over-
flow.
[7] Reserved.
IOC I Overcurrent.
[9] Reserved.
VSAG Voltage channel sag event detected.
TUP Temperature updated. Indicates when the Temperature register (T) has been updated.
FUP Frequency updated. Indicates the Epsilon register has been updated.
IC Invalid command has been received.
RX_CSUM_ERR Received data checksum error. Sets to one automatically if checksum error is detected on
serial port received data.
RX_TO SDI/RX time out. Sets to one automatically when SDI/RX time out occurs.
23 22 21 20 19 18 17 16
DRDY CRDY WOF - - MIPS - VSWELL
15 14 13 12 11 10 9 8
- POR - IOR - VOR - IOC
76543 2 10
- VSAG TUP FUP IC RX_CSUM_ERR -
RX_TO