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Cirrus Logic, Inc.

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CS5484

Four Channel Energy Measurement IC

Features & Description

• Superior Analog Performance with Ultra-low Noise Level

and High SNR

• Energy Measurement Accuracy of 0.1% over 4000:1

Dynamic Range

• Current RMS Measurement Accuracy of 0.1% over 1000:1

Dynamic Range

• 4 Independent 24-bit, 4

-order, Delta-Sigma Modulators

for Voltage and Current Measurements

• 4 Configurable Digital Outputs for Energy Pulses,

Zero-crossing, or Energy Direction

• Supports Shunt Resistor, CT, and Rogowski Coil Current

Sensors

• On-chip Measurements/Calculations:

- Active, Reactive, and Apparent Power

- RMS Voltage and Current

- Power Factor and Line Frequency

- Instantaneous Voltage, Current, and Power

• Overcurrent, Voltage Sag, and Voltage Swell Detection

• Ultra-fast On-chip Digital Calibration

• Internal Register Protection via Checksum and Write

Protection

• UART/SPI™ Serial Interface

• On-chip Temperature Sensor

• On-chip Voltage Reference (25ppm/°C Typ.)

• Single 3.3V Power Supply

• Ultra-fine Phase Compensation

• Low Power Consumption: <13mW

• Power Supply Configurations

- GNDA = GNDD = 0V, VDDA = +3.3V

• 5mmx5mm 28-pin QFN Package

ORDERING INFORMATION

See Page 68.

Description

The CS5484 is a high-accuracy, four-channel, energy

measurement analog front end.

The CS5484 incorporates independent 4

order Delta-Sigma

analog-to-digital converters for every channel, reference

circuitry, and the proven EXL signal processing core to provide

active, reactive, and apparent energy measurement. In

addition, RMS and power factor calculations are available.

Calculations are output through a configurable energy pulse,

or direct UART/SPI™ serial access to on-chip registers.

Instantaneous current, voltage, and power measurements are

also available over the serial port. Multiple serial options are

offered to allow customer flexibility. The SPI provides higher

speed, and the 2-wire UART minimizes the cost of isolation

where required.

Four configurable digital outputs provide energy pulses,

zero-crossing, energy direction, and interrupt functions.

Interrupts can be generated for a variety of conditions

including voltage sag or swell, overcurrent, and more. On-chip

The CS5484 is designed to interface to a variety of voltage and

current sensors including shunt resistors, current

transformers, and Rogowski coils.

On-chip functionality makes digital calibration simple and

ultra-fast, minimizing the time required at the end of the

customer production line. Performance across temperature is

ensured with an on-chip voltage reference with low drift. A

single 3.3V power supply is required, and power consumption

is low at <13mW. To minimize space requirements, the

CS5484 is offered in a low-cost, 5mm x5mm 28-pin QFN

package.

VDDA

TX / SDO

RX / SDI

UART/SPI

Serial

Interface

Configurable

Digital

Outputs

RESET

Calculation

Order 

Modulator

HPF

Option

DO1

DO2

HPF

Option

VREF+

VDDD

VREF-

System

Clock

IIN2+

IIN2-

PGA

IIN1+

IIN1-

PGA

10x

CS5484

SCLK

SSEL

DO3

VIN1+

VIN1-

10x

VIN2+

VIN2-

Digital

Filter

Digital

Filter

DO4

MODE

HPF

Option

Digital

Filter

HPF

Option

Digital

Filter

Order 

Modulator

Order 

Modulator

Order 

Modulator

GNDA GNDD

Voltage

Reference

Temperature

Sensor

XIN XOUT

CPUCLK

Clock

Generator

MAR’13

DS981F3

Summary of content (67 pages)

PAGE 1
CS5484 Four Channel Energy Measurement IC Features & Description Description • The CS5484 is a high-accuracy, four-channel, energy measurement analog front end. • • • • • • • • • • • • • • • • • Superior Analog Performance with Ultra-low Noise Level and High SNR Energy Measurement Accuracy of 0.1% over 4000:1 Dynamic Range Current RMS Measurement Accuracy of 0.
PAGE 2
CS5484 TABLE OF CONTENTS 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.1 Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
CS5484 5.7 Phase Sequence Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9 Anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10.
PAGE 4
CS5484 LIST OF FIGURES Figure 1. Oscillator Connections................................................................................................... 7 Figure 2. Multi-device UART Connections.................................................................................... 8 Figure 3. UART Serial Frame Format ........................................................................................... 8 Figure 4. Active Energy Load Performance............................................................
PAGE 5
CS5484 1. OVERVIEW The CS5484 is a CMOS power measurement integrated circuit using four  analog-to-digital converters to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temperature measurement. It calculates active, reactive, and apparent power as well as RMS voltage and current and peak voltage and current.
PAGE 6
CS5484 XOUT VDDD GNDD CPUCLK MODE SSEL CS 2.
PAGE 7
CS5484 2.1 Analog Pins The CS5484 has two differential inputs (VIN1VIN2) for voltage input and two differential inputsIIN1 IIN2) for current1 and current2 inputs. The CS5484 also has two voltage reference pins (VREF) between which a bypass capacitor should be placed. XIN XOUT 2.1.1 Voltage Inputs The output of the line voltage resistive divider or transformer is connected to the VIN1 or VIN2 input pins of the CS5484. The voltage channel is equipped with a 10x, fixed-gain amplifier.
PAGE 8
CS5484 2.2.4 UART/SPI™ Serial Interface The CS5484 provides five pins—SSEL, RX/SDI, TX/SDO, CS, and SCLK—for communication between a host microcontroller and the CS5484. requires a separate CS signal for enabling communication to that slave. The multi-device UART mode connections are shown in Figure 2. SLAVE 0 SSEL is an input that, when low, indicates to the CS5484 to use the SPI port as the serial interface to communicate with the host microcontroller. The SSEL pin has an internal weak pull-up.
PAGE 9
CS5484 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Positive Analog Power Supply Specified Temperature Range Symbol VDDA TA Min 3.0 -40 Typ 3.3 - Max 3.6 +85 Unit V °C POWER MEASUREMENT CHARACTERISTICS Parameter Active Energy (Note 1 and 2) Reactive Energy (Note 1 and 2) Apparent Power (Note 1 and 3) Current RMS (Note 1, 3, and 4) Symbol Min Typ Max Unit All Gain Ranges Current Channel Input Signal Dynamic Range 4000:1 PAvg - ±0.
PAGE 10
CS5484 1 Percent Error (%) 0.5 0 Lagging sin(੮) = 0.5 Leading sin(੮) = 0.5 sin(੮) = 1 -0.5 -1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Current Dynamic Range (x : 1) Figure 5. Reactive Energy Load Performance 1 Percent Error (%) 0.5 0 IRMS Error IRMS Error -0.5 -1 0 500 1000 1500 Current Dynamic range (x : 1) Figure 6.
PAGE 11
CS5484 ANALOG CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. MCLK = 4.096MHz.
PAGE 12
CS5484 Parameter Symbol Min Typ Max Unit PSCA - 3.9 - mA PC - 12.9 4.5 - mW mW Power Supplies Power Supply Currents (Active State) IA+ (VDDA = +3.3V) Power Consumption (Note 5) Notes: Active State (VDDA = +3.3V) Stand-by State 5. 6. 7. All outputs unloaded. All inputs CMOS level. Temperature accuracy measured after calibration is performed. Measurement method for PSRR: VDDA = +3.3V, a 150mV (zero-to-peak) (60Hz) sine wave is imposed onto the +3.3V DC supply voltage at the VDDA pin.
PAGE 13
CS5484 DIGITAL CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. MCLK = 4.096MHz.
PAGE 14
CS5484 SWITCHING CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C. VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V. Logic Levels: Logic 0 = 0V, Logic 1 = VDDA. Parameter Symbol Min Typ Max Unit DO1-DO4 Any Digital Output Except DO1-DO4 trise - 50 1.
PAGE 15
CS5484 CS t6 t1 t3 SCLK t2 t7 SDO MSB t4 SDI t8 MSB-1 LSB INTERMEDIATE BITS t5 MSB MSB-1 INTERMEDIATE BITS LSB Figure 7. SPI Data and Clock Timing CS t10 t9 TX RX START IDLE START LSB DATA MSB STOP IDLE LSB DATA MSB OPTIONAL OVERLAP INSTRUCTION * t11 IDLE STOP STOP * Reading registers during the optional overlap instruction requires the start to occur during the last byte transmitted by the part Figure 8.
PAGE 16
CS5484 ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Input Current (Note 16) (Notes 17 and 18) Input Current for Power Supplies Symbol Min Typ Max Unit VDDA -0.3 - +4.0 V IIN - - ±10 mA - - - ±50 - Output Current (Note 19) IOUT - - 100 mA Power Dissipation (Note 20) PD - - 500 mW Input Voltage (Note 21) VIN - 0.3 - (VDDA) + 0.
PAGE 17
PMF 4th Order ΔΣ Modulator x10 DELAY CTRL SINC3 IIR X +  X + V1DCOFF PC ... CPCC1[1:0] ... FPCC1[8:0] ... V1GAIN SYSGAIN Config 2 I1 DCOFF IIN1± 4th Order ΔΣ Modulator PGA V1 HPF DELAY CTRL SINC3 IIR X + ... V1FLT[1:0] I1FLT[1:0] Phase Shift X Epsilon X ... X Q1 2 X I1 GAIN P1 +  HPF X INT MUX VIN1± MUX CS5484 PMF I1 Registers Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements 4.
PAGE 18
CS5484 Fine phase compensation control bits, FPCCx[8:0], provide up to 1/OWR delay in the current channel. Coarse phase compensation control bits, CPCCx[1:0], provide an additional 1/OWR delay in the current channels or up to 2/OWR delay in the voltage channel. Negative delay in the voltage channel can be implemented by setting longer delay in the current channel than the voltage channel. For a OWR of 4000Hz, the delay range is ±500µs, a phase shift of ±8.99° at 50Hz and ±10.79° at 60 Hz.
PAGE 19
CS5484 4.8.2 Line-cycle Synchronized Averaging 4.8.5 Reactive Power When operating in Line-cycle Synchronized Averaging mode, and when line frequency measurement is enabled (see section 5.4 Line Frequency Measurement on page 22), the CS5484 uses the voltage (V) channel zero crossings and measured line frequency to automatically adjust N such that the averaging period will be equal to the number of half line-cycles in the CycleCount register.
PAGE 20
CS5484 4.9 Average Active Power Offset 4.10 Average Reactive Power Offset The average active power offset registers, P1OFF (P2OFF), can be used to offset erroneous power sources resident in the system not originating from the power line. Residual power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer.
PAGE 21
CS5484 5. FUNCTIONAL DESCRIPTION 5.1 Power-on Reset Table 1. POR Thresholds The CS5484 has an internal power supply supervisor circuit that monitors the VDDA and VDDD power supplies and provides the master reset to the chip. If any of these voltages are in the reset range, the master reset is triggered. The CS5484 has dedicated power-on reset (POR) circuits for the analog supply and digital supply. During power-up, both supplies have to be above the rising threshold for the master reset to be de-asserted.
PAGE 22
CS5484 V(t), I(t) If |VPEAK| > VZXLEVEL, then voltage zero-crossing detection is enabled. If |IPEAK| > IZXLEVEL, then current zero-crossing detection is enabled. If |VPEAK| VZXLEVEL, then voltage zero-crossing detection is disabled. If |IPEAK| IZXLEVEL, then current zero-crossing detection is disabled. VZXLEVEL IZXLEVEL t DOx Zero-crossing output on DOx pin Pulse width = 250μs t Figure 13. Zero-crossing Level and Zero-crossing Output on DOx 5.
PAGE 23
CS5484 EPGx_ON (Config1) MCLK 0001 0001 P SUM 0010 Q SUM 0101 S1 AVG 0110 S2 AVG 0111 S SUM 1000 PULSE RATE P1 Sign 0100 P2 Sign 0101 P SUM Sign 0110 Q1 Sign 0111 Q2 Sign 1000 QSUM Sign 1001 RESERVED 1010 V1/V2 Crossing 1011 I1/I2 Crossing 1100 RESERVED 1101 Hi-Z Interrupt (PulseCtrl) EPGxIN[3:0] 4 (PulseWidth) FREQ_RNG[3:0] 4 (PulseWidth) PW[7:0] 8 1110 DO2_OD (Config1) DO2 Digital Output Mux (DO4) 0100 0011 Digital Output Mux (DO3) Q2AVG DO1 0010 Digital O
PAGE 24
CS5484 5.5.1 Pulse Rate Before configuring the PulseRate register, the full-scale pulse rate needs to be calculated and the frequency range needs to be specified through FREQ_RNG[3:0] bits in the PulseWidth register. Refer to section 6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8 on page 41. The FREQ_RNG[3:0] bits should be set to b[0110].
PAGE 25
CS5484 5.7 Phase Sequence Detection Polyphase meters using multiple CS5484 devices may be configured to sense the succession of voltage zero-crossings and determine which phase order is in service. The phase sequence detection within CS5484 involves counting the number of OWR samples from a starting point to the next voltage zero-crossing rising edge or falling for each phase.
PAGE 26
CS5484 Write 0x16 to PSDC Register Start on the Falling Edge on the RX Pin Phase A Channel Stop 2 Phase A Count 0 -2 C Phase B Channel Stop 2 Phase B Count 0 -2 A B Phase C Channel Stop 2 Phase C Count 0 -2 Figure 17. Phase Sequence C, B, A for Rising Edge Transition The temperature sensor and V2 input share the same delta-sigma modulator on the second voltage channel. By default, the temperature measurement is disabled, and the delta-sigma modulator is used for V2 measurement.
PAGE 27
CS5484 6. HOST COMMANDS AND REGISTERS 6.1.1.2 Register Read 6.1 Host Commands A register read is designated by setting the two MSBs of the command to binary ‘00’. The lower 6 bits of the register read command are the lower 6 bits of the 12-bit register address. After the register read command has been received, the CS5484 will send 3 bytes of register data onto the SDO/TX pin. The first byte sent to the CS5484 SDI/RX pin contains the host command.
PAGE 28
CS5484 Table 3. Instruction Format Function Controls Binary Value 0 C4 C3 C2 C1 C0 0 00001 - Software Reset 0 00010 - Standby 0 00011 - Wakeup 0 10100 - Single Conv. 0 10101 - Continuous Conv. 0 11000 - Halt Conv. 1 C4 C3 C2 C1 C0 1 00 1 10 1 11 Calibrations C2C1C0 C2C1C0 C2C1C0 DC Offset AC Offset* Gain Note C[5] specifies the instruction type: 0 = Controls 1 = Calibrations For calibrations, C[4:3] specifies the type of calibration.
PAGE 29
CS5484 6.
PAGE 30
CS5484 53 54 55 56 57 58 59 60 61 62 63 Notes: 30 11 0101 11 0110 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 ZXNUM - Reserved Reserved Num. Zero Crosses used for Line Freq. Y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Y 0x00 0064 - (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST.
PAGE 31
CS5484 6.
PAGE 32
CS5484 53 54* 55* 56* 57 58* 59* 60* 61 62 63 Notes: 11 0101 11 0110 11 0111 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 TGAIN TOFF TSETTLE LoadMIN SYSGAIN Time - Reserved Temperature Gain Temperature Offset Reserved Filter Settling Time to Conv.
PAGE 33
CS5484 6.
PAGE 34
CS5484 6.
PAGE 35
CS5484 6.6 Register Descriptions 1. 2. 3. 4. “Default” = bit states after power-on or reset DO NOT write a “1” to any unpublished register bit or to a bit published as “0”. DO NOT write a “0” to any bit published as “1”. DO NOT write to any unpublished register address. 6.6.
PAGE 36
CS5484 NO_OSC Disable crystal oscillator (making XIN a logic-level input). 0 = Crystal oscillator enabled (Default) 1 = Crystal oscillator disabled IZX_CH Select current channel for zero-cross detect. 0 = Selects current channel 1 for zero-cross detect (Default) 1 = Selects current channel 2 for zero-cross detect VZX_CH Selects voltage channel for zero-cross detect. 0 = Selects voltage channel 1 for zero-cross detect (Default) 1 = Selects voltage channel 2 for zero-cross detect 6.6.
PAGE 37
CS5484 DO4MODE[3:0] Output control for DO4 pin.
PAGE 38
CS5484 DO1MODE[3:0] Output control for DO1 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Energy pulse generation block 4 (EPG4) output 0100 = P1 sign 0101 = P2 sign 0110 = PSUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = QSUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt 6.6.
PAGE 39
CS5484 AFC Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is used to control the gain of 90 degree phase shift integrator used in quadrature power calculations. 0 = Disable automatic line frequency measurement 1 = Enable automatic line frequency measurement (Default) I2FLT[1:0] Filter enable for current channel 2.
PAGE 40
CS5484 6.6.4 Phase Compensation (PC) – Page 0, Address 5 23 CPCC2[1] 22 CPCC2[0] 21 CPCC1[1] 20 CPCC1[0] 19 - 18 - 17 FPCC2[8] 16 FPCC2[7] 15 FPCC2[6] 14 FPCC2[5] 13 FPCC2[4] 12 FPCC2[3] 11 FPCC2[2] 10 FPCC2[1] 9 FPCC2[0] 8 FPCC1[8] 7 6 5 4 3 2 1 0 FPCC1[7] FPCC1[6] FPCC1[5] FPCC1[4] FPCC1[3] FPCC1[2] FPCC1[1] FPCC1[0] Default = 0x00 0000 CPCC2[1:0] Coarse phase compensation control for I2 and V2.
PAGE 41
CS5484 6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8 23 - 22 - 21 - 20 - 19 18 17 16 FREQ_RNG[3] FREQ_RNG[2] FREQ_RNG[1] FREQ_RNG[0] 15 PW[15] 14 PW[14] 13 PW[13] 12 PW[12] 11 PW[11] 10 PW[10] 9 PW[9] 8 PW[8] 7 6 5 4 3 2 1 0 PW[7] PW[6] PW[5] PW[4] PW[3] PW[2] PW[1] PW[0] Default = 0x00 0001 (265.6µs at OWR = 4kHz) PulseWidth sets the energy pulse frequency range and the duration of energy pulses.
PAGE 42
CS5484 6.6.8 Pulse Output Control (PulseCtrl) – Page 0, Address 9 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 EPG4IN[3] 14 EPG4IN[2] 13 EPG4IN[1] 12 EPG4IN[0] 11 EPG3IN[3] 10 EPG3IN[2] 9 EPG3IN[1] 8 EPG3IN[0] 7 6 5 4 3 2 1 0 EPG2IN[3] EPG2IN[2] EPG2IN[1] EPG2IN[0] EPG1IN[3] EPG1IN[2] EPG1IN[1] EPG1IN[0] Default = 0x00 0000 This register controls the input to the energy pulse generation block (EPGx). [23:16] Reserved.
PAGE 43
CS5484 6.6.10 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48 23 DONE 22 PSCNT[6] 21 PSCNT[5] 20 PSCNT[4] 19 PSCNT[3] 18 PSCNT[2] 17 PSCNT[1] 16 PSCNT[0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 DIR 4 CODE[4] 3 CODE[3] 2 CODE[2] 1 CODE[1] 0 CODE[0] Default = 0x00 0000 DONE Indicates valid count values reside in PSCNT[6:0]. 0 = Invalid values in PSCNT[6:0]. (Default) 1 = Valid values in PSCNT[6:0].
PAGE 44
CS5484 6.6.12 Interrupt Status (Status0) – Page 0, Address 23 23 DRDY 22 CRDY 21 WOF 20 - 19 - 18 MIPS 17 V2SWELL 16 V1SWELL 15 P2OR 14 P1OR 13 I2OR 12 I1OR 11 V2OR 10 V1OR 9 I2OC 8 I1OC 7 V2SAG 6 V1SAG 5 TUP 4 FUP 3 IC 2 RX_CSUM_ERR 1 - 0 RX_TO Default = 0x80 0000 The Status0 register indicates a variety of conditions within the chip. Writing a one to a Status0 register bit will clear that bit. Writing a zero to any bit has no effect. DRDY Data Ready.
PAGE 45
CS5484 6.6.13 Interrupt Mask (Mask) – Page 0, Address 3 23 DRDY 22 CRDY 21 WOF 20 - 19 - 18 MIPS 17 V2SWELL 16 V1SWELL 15 P2OR 14 P1OR 13 I2OR 12 I1OR 11 V2OR 10 V1OR 9 I2OC 8 I1OC 7 V2SAG 6 V1SAG 5 TUP 4 FUP 3 IC 2 RX_CSUM_ERR 1 - 0 RX_TO Default = 0x00 0000 The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow the corresponding Status0 register bit to activate the INT pin when set.
PAGE 46
CS5484 6.6.15 Chip Status 2 (Status2) – Page 0, Address 25 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 QSUM_SIGN 4 Q2_SIGN 3 Q1_SIGN 2 PSUM_SIGN 1 P2_SIGN 0 P1_SIGN Default = 0x00 0000 This register indicates a variety of conditions within the chip. 46 [23:6] Reserved. QSUM_SIGN Indicates the sign of the value contained in QSUM. 0 = positive value 1 = negative value Q2_SIGN Indicates the sign of the value contained in Q2AVG.
PAGE 47
CS5484 6.6.16 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x01 999A (0.0125 or 50Hz/4.0kHz) Epsilon is the ratio of the input line frequency to the OWR. It can either be written by the application program or calculated automatically from the line frequency (from the voltage channel 1 input) using the AFC bit in the Config2 register.
PAGE 48
CS5484 6.6.20 Filter Settling Time for Conversion Startup (TSETTLE) – Page 16, Address 57 MSB 223 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 001E (30) Sets the number of OWR samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands. This is an integer in the range of 0 to 16,777,215 samples. 6.6.21 System Gain (SysGAIN ) – Page 16, Address 60 MSB -(21) LSB 20 2-1 2-2 2-3 2-4 2-5 2-6 .....
PAGE 49
CS5484 6.6.24 Voltage 1 Sag Duration (V1SagDUR ) – Page 17, Address 0 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage sag duration, V1SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.25 Voltage 1 Sag Level (V1SagLEVEL ) – Page 17, Address 1 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 .....
PAGE 50
CS5484 6.6.28 Voltage 2 Sag Duration (V2SagDUR ) – Page 17, Address 8 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage sag duration, V2SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.29 Voltage 2 Sag Level (V2SagLEVEL ) – Page 17, Address 9 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 .....
PAGE 51
CS5484 6.6.32 Voltage 1 Swell Duration (V1SwellDUR ) – Page 18, Address 46 MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x00 0000 Voltage swell duration, V1SwellDUR, determines the count of OWR samples utilized to determine a swell event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. 6.6.33 Voltage 1 Swell Level (V1SwellLEVEL ) – Page 18, Address 47 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 .....
PAGE 52
CS5484 6.6.36 Instantaneous Current 1 (I1) – Page 16, Address 2 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 I1 contains instantaneous current measurements for current channel 1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.37 Instantaneous Voltage 1 (V1) – Page 16, Address 3 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 .....
PAGE 53
CS5484 6.6.40 RMS Current 1 (I1RMS ) – Page 16, Address 6 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24 Default = 0x00 0000 I1RMS contains the root mean square (RMS) values of I1, calculated during each low-rate interval. This is an unsigned value in the range of 0  value  1.0, with the binary point to the left of the MSB. 6.6.41 RMS Voltage 1 (V1RMS ) – Page 16, Address 7 MSB 2-1 LSB 2-2 2-3 2-4 2-5 2-6 2-7 2-8 .....
PAGE 54
CS5484 6.6.44 Instantaneous Active Power 2 (P2) – Page 16, Address 10 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 P2 contains instantaneous power measurements for current and voltage channels 2. Values in registers I2 and V2 are multiplied to generate this value. This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. 6.6.
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CS5484 6.6.48 Reactive Power 1 (Q1Avg ) – Page 16, Address 14 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Reactive power 1 (Q1AVG) is Q1 averaged over each low-rate interval (SampleCount samples) and corrected by QOFF. This is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. 6.6.
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CS5484 6.6.52 Peak Current 1 (I1PEAK) – Page 0, Address 37 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak current1 (I1PEAK) contains the value of the instantaneous current 1 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0  value 1.0, with the binary point to the right of the MSB. 6.6.
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CS5484 6.6.56 Peak Current 2 (I2PEAK) – Page 0, Address 39 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Peak current, I2PEAK, contains the value of the instantaneous current 2 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. 6.6.
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CS5484 6.6.60 Temperature (T) – Page 16, Address 27 MSB -(27) LSB 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Default = 0x00 0000 T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale and is a two's complement value in the range of -128.0value128.0 (°C), with the binary point to the right of bit 16. T can be rescaled by the application using the TGAIN and TOFF registers. 6.6.
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CS5484 6.6.64 DC Offset for Current (I1DCOFF , I2DCOFF ) – Page 16, Address 32, 39 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 DC offset registers I1DCOFF and I2DCOFF are initialized to zero on reset. During DC offset calibration, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.
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CS5484 6.6.68 Average Active Power Offset (P1OFF, P2OFF ) – Page 16, Address 36, 43 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23 Default = 0x00 0000 Average Active Power offset P1OFF (P2OFF ) is added to averaged power to yield P1AVG (P2AVG ) register results. It can be used to reduce systematic energy errors. These are two's complement values in the range of -1.0 value 1.0, with the binary point to the right of the MSB. 6.6.
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CS5484 6.6.72 Temperature Offset (TOFF ) – Page 16, Address 55 MSB LSB -(27) 26 25 24 23 22 21 20 ..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Default = 0x D5 3998 Register TOFF is used to offset the Temperature register (T), and is a two's complement value in the range of -128.0value128.0 (°C), with the binary point to the right of bit 16. Register T can be rescaled by the application using the TGAIN and TOFF registers. Refer to section 7.
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CS5484 7. SYSTEM CALIBRATION commands. The value in the SampleCount register determines the number (N) of output word rate (OWR) samples that are averaged during a calibration. The calibration procedure takes the time of N+TSETTLE OWR samples. As N is increased, the calibration takes more time, but the accuracy of the calibration results tends to increase. Component tolerances, residual ADC offset, and system noise require a meter that needs to be calibrated before it meets a specific accuracy requirement.
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CS5484 7.1.1.2 AC Offset Calibration The AC offset calibration command measures the residual RMS values on the current channel at zero input and stores the squared result in the associated AC offset register. This AC offset will be subtracted from RMS measurements in subsequent conversions, removing the AC offset on the associated current channel. The AC offset register for the channel being calibrated should first be cleared prior to performing the calibration.
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CS5484 3) Accumulate multiple readings of the PF1 or PF2 register. 4) Calculate the average power factor, PFavg. 5) Calculate phase offset = arccos(PFavg) - 60°. 6) If the phase offset is negative, then the delay should be added only to the current channel. Otherwise, add more delay to the voltage channel than to the current channel to compensate for a positive phase offset. 7.3.
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CS5484 8. BASIC APPLICATION CIRCUITS Figure 25 shows the CS5484 configured to measure power in a single-phase, 3-wire system with two voltages and two currents. In this diagram, current transformers (CTs) are used to sense the line load currents, and resistive voltage dividers are used to sense the line voltage. +3.3V +3.3V 0.1uF L1 N 0.1uF Wh VDDA MODE VDDD L2 VIN1+ Varh +3.
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CS5484 9. PACKAGE DIMENSIONS 28 QFN (5mmX5mm BODY with EXPOSED PAD) PACKAGE DRAWING Dimension A A1 A3 b D D2 e E E2 L aaa bbb ddd eee MIN 0.80 0.00 0.20 3.50 3.50 0.35 mm NOM 0.90 0.02 0.20 REF 0.25 5.00 BSC 3.65 0.50 BSC 5.00 BSC 3.65 0.40 0.15 0.10 0.05 0.08 MAX 1.00 0.05 MIN 0.031 0.000 0.30 0.008 3.80 0.138 3.80 0.45 0.138 0.014 inch NOM 0.035 0.001 0.008 REF 0.010 0.197 BSC 0.144 0.020 BSC 0.197 BSC 0.144 0.016 0.006 0.004 0.002 0.003 MAX 0.039 0.002 0.012 0.150 0.150 0.018 Notes: 1.
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CS5484 10. ORDERING INFORMATION Ordering Number Container CS5484-INZ Bulk CS5484-INZR Tape & Reel Temperature Package -40 to +85 °C 28-pin QFN, Lead (Pb) Free 11. ENVIRONMENTAL, MANUFACTURING, AND HANDLING INFORMATION Part Number Peak Reflow Temp MSL Rating* Max Floor Life CS5484-INZ 260°C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 12. REVISION HISTORY Revision Date PP1 APR 2012 Changes Preliminary release.