User guide

CS5480
46 DS980F3
6.6.13 Interrupt Status (Status0) – Page 0, Address 23
Default = 0x80 0000
The Status0 register indicates a variety of conditions within the chip.
Writing a one to a Status0 register bit will clear that bit. Writing a ‘0’ to any bit has no effect.
DRDY Data Ready.
During conversion, this bit indicates that low-rate results have been updated.
It indicates completion of other host instruction and the reset sequence.
CRDY Conversion Ready.
Indicates that sample rate (output word rate) results have been updated.
WOF Watchdog timer overflow.
[20:19] Reserved.
MIPS MIPS overflow.
Sets when the calculation engine has not completed processing a sample before the
next one arrives.
V2SWELL (V1SWELL) V2 (V1) swell event detected.
P2OR (P1OR) Power out of range.
Sets when the measured power would cause the P2 (P1) register to overflow.
I2OR (I1OR) Power out of range.
Sets when the measured current would cause the I2 (I1) register to overflow.
V2OR (V1OR) Voltage out of range.
Sets when the measured current would cause the V2 (V1) register to overflow.
I2OC (I1OC) I2 (I1) overcurrent.
V2SAG (V1SAG) V2 (V1) sag event detected.
TUP Temperature updated.
Indicates when the Temperature register (T) has been updated.
FUP Frequency updated.
Indicates the Epsilon register has been updated.
IC Invalid command has been received.
RX_CSUM_ERR Received data checksum error.
Sets to ‘1’ automatically if checksum error is detected on serial port received data.
[1] Reserved.
RX_TO SDI/RX time out.
Sets to ‘1’ automatically when SDI/RX time out occurs.
23 22 21 20 19 18 17 16
DRDY CRDY WOF - - MIPS V2SWELL V1SWELL
15 14 13 12 11 10 9 8
P2OR P1OR I2OR I1OR V2OR V1OR I2OC I1OC
76543 2 10
V2SAG V1SAG TUP FUP IC RX_CSUM_ERR -
RX_TO