User Manual

CS5463

26 DS678F3

6. REGISTER DESCRIPTION

1. “Default” = bit stat us after power-on or reset

2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.

6.1 Page 0 Registers

6.1.1 Configuration Register ( Config )

Address: 0

Default = 0x000001

PC[6:0] Phase compensation. A 2’s complement number which sets a delay in the voltage chan nel rel-

ative to the curr ent channe l. Defa ult setting is 0 000000 = 0.0215 degree phase de lay at 60 Hz

(when MCLK = 4.09 6 MH z). See Sec t io n 7.2

Phase Compensation on page 39 for more infor-

mation.

gain

Sets the gain of the current PGA.

0 = Gain is 10 (default)

1 = Gain is 50

EWA Allows the E1

and E2 pins to be configured as open-collector output pins.

0 = Normal outputs (default)

1 = Only the pull-down device of the E1

and E2 pins are active

IMODE, IINV Interrupt configuration bits. Select the desired pin beh avior for indication of an interrupt.

00 = Active-low level (default)

01 = Active-high level

10 = High-to-low pulse

11 = Low-to-high pulse

iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present wh en analog signals

are sampled, the logic dr ive n by CPUC LK sh ould not be activ e du rin g the samp le edge.

0 = Normal operation (default)

1 = Minimize noise when CPUCLK is driving rising edge logic

K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal

clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-

tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K = 1 at reset.

23 22 21 20 19 18 17 16

PC6 PC5 PC4 PC3 PC2 PC1 PC0 Igain

15 14 13 12 11 10 9 8

EWA - - IMODE IINV - - -

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