CS5463 Single Phase, Bi-directional Power/Energy IC Features Description Energy The CS5463 is an integrated power measurement device which combines two analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip.
CS5463 TABLE OF CONTENTS 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS5463 6.1.7 Active (Real) Power Register ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.8 RMS Current & Voltage Registers ( IRMS , VRMS ) . . . . . . . . . . . . . . . . . . 6.1.9 Epsilon Register ( e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.10 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.11 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . 6.1.
CS5463 LIST OF FIGURES Figure 1. CS5463 Read and Write Timing Diagrams.................................................................. 12 Figure 2. Timing Diagram for E1, E2, and E3....................................................................................... 13 Figure 3. Data Measurement Flow Diagram. .............................................................................. 14 Figure 4. Power Calculation Flow. .................................................................................
CS5463 1. OVERVIEW The CS5463 is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5463 combines a programmable gain amplifier, two Analog-to-Digital Converters (ADCs), system calibration, and a computation engine on a single chip.
CS5463 2.
CS5463 3. CHARACTERISTICS & SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VD+ VA+ VREFIN TA Min 3.135 4.75 -40 Typ 5.0 5.0 2.5 - Max 5.25 5.25 +85 Unit V V V °C ANALOG CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
CS5463 ANALOG CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Unit Analog Inputs (Voltage Channel) Differential Input Range [(VIN+) - (VIN-)] VIN - 500 - mVP-P Total Harmonic Distortion Crosstalk with Current Channel at Full Scale (50, 60 Hz) Input Capacitance All Gain Ranges Effective Input Impedance Noise (Referred to Input) THD IC EII NV 65 2 - 75 -70 0.2 140 - dB dB pF M µVrms Offset Drift (Without the High Pass Filter) Gain Error OD GE - 16.0 ±3.
CS5463 VOLTAGE REFERENCE Parameter Symbol Min Typ Max Unit VREFOUT +2.4 +2.5 +2.6 V Reference Output Output Voltage Temperature Coefficient (Note 8) TCVREF - 25 60 ppm/°C Load Regulation (Note 9) VR - 6 10 mV VREFIN +2.4 +2.5 +2.6 V Input Capacitance - 4 - pF Input CVF Current - 25 - nA Reference Input Input Voltage Range Notes: 8. The voltage at VREFOUT is measured across the temperature range.
CS5463 Parameter Symbol Min Typ Max Unit Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL - - 0.48 0.3 0.2VD+ V V V High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V Low-level Output Voltage Iout = -5 mA VOL - - 0.4 V Iin - ±1 ±10 µA 3-state Leakage Current IOZ - - ±10 µA Digital Output Pin Capacitance Cout - 5 - pF Input Leakage Current (Note 16) Notes: 10.
CS5463 SWITCHING CHARACTERISTICS • • • • Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
CS5463 t3 CS t1 t2 SC LK H ig h B y te LSB MSB MSB-1 LSB LSB MSB MSB C o m m a n d T im e 8 S C L K s MSB-1 t5 MSB-1 LSB SDI MSB-1 MSB t4 M id B y te L o w B y te SDI Write Timing (Not to Scale) CS t1 t8 LSB MSB-1 LSB MSB L o w B y te MSB-1 LSB UNKNOW N MSB-1 MSB SDO M id B y te MSB H ig h B y te t6 t7 t2 LSB MSB-1 SDI MSB SC LK C o m m a n d T im e 8 S C L K s SYN C 0 or SYN C 1 C om m and SYN C 0 or SYN C1 C om m and SYN C 0 or SYN C1 C om m and SDO Read
CS5463 SWITCHING CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Unit tperiod 250 - - s Pulse Width tpw 244 - - s Rising Edge to Falling Edge t3 6 - - s E2 Setup to E1 and/or E3 Falling Edge t4 1.5 - - s E1 Falling Edge to E3 Falling Edge t5 248 - - s E1, E2, and E3 Timing (Note 19 and 20) Period Notes: 19. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to Section 5.
VDCoff* Vgn * VOLTAGE x10 DELAY REG SINC 3 X DELAY REG IIR MUX Digital Filter 2nd Order Modulator + APF + MUX CS5463 V* HPF HPF X VQ* X 6 * PC6 PC5 PC4 PC3 PC2 PC1 PC0 SYSGain * Configuration Register * 4th Order Modulator SINC 3 8 6 7 IHPF 5 IIR 4 X DELAY REG IIR Digital Filter + X IDCoff* Q* X P* X + X + 2 Operational Modes Register * DELAY REG 3 2 1 0 HPF APF MUX PGA XVDEL XIDEL VHPF MUX CURRENT 2322 ...
CS5463 VACoff* N V* X ÷N + + V RMS* IACoff* N I* X Poff * PulseRate * X Energy-to-pulse + P* + ÷N N N Q* + S* + X X I RMS* E1 ÷N - + E2 Inverse X QTRIG* PF* E3 PACTIVE* X ÷N QAVG* *DENOTES REGISTER NAME. Figure 4. Power Calculation Flow. provides a pulse output that is proportional to the reactive power or apparent power.
CS5463 5. FUNCTIONAL DESCRIPTION 5.1 Analog Inputs The CS5463 is equipped with two fully differential input channels. The inputs VIN and IIN are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 250 mVP. 5.1.1 Voltage Channel The output of the line voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of the CS5463.
CS5463 for unsigned registers is a normalized value between 0 and 1. A register value of the pulse output mode, which is controlled by bit E2MODE in the Operational Mode Register. 23 2 – 1 ------------------------ = 0.99999988 23 2 represents the maximum possible value. At each instantaneous measurement, the CRDY bit will be set in the Status Register, and the INT pin will become active if the CRDY bit is unmasked in the Mask Register.
CS5463 The pulse output frequency of E1 is directly proportional to the active power calculated from the input signals.
CS5463 Output pin E3 is high when the line voltage is positive and pin E3 is low when the line voltage is negative. 5.5.5 PFMON Output Mode Setting bit E3MODE[1:0] = 1 (01b) in the Operational Mode Register outputs the state of the PFMON comparator on pin E3. Figure 8 illustrates the output format with PFMON on E3 E1 E2 E3 Above PFMON Threshold Below PFMON Threshold Figure 8.
CS5463 The temperature update rate is a function of the number of ADC samples. With MCLK = 4.096 MHz and K = 1 the update rate is: 2240 samples --------------------------------------- = MCLK K 1024 0.56 sec The Cycle Count Register (N) must be set to a value greater then one. Status bit TUP in the Status Register, indicates when the Temperature Register is updated. The Temperature Offset Register sets the zero-degree measurement.
CS5463 drive the device from an external clock source, XOUT should be left unconnected while XIN is driven by the external circuitry. There is an amplifier between XIN and the digital section which provides CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. INTERRUPT HANDLER ROUTINE: 4) Read the Status Register. 5) Disable all interrupts. 6) Branch to the proper interrupt service routine.
CS5463 If the serial port interface becomes unsynchronized with respect to the SCLK input, any attempt to clock valid commands into the serial interface may result in unexpected operation. Therefor, the serial port interface must then be re-initialized by one of the following actions: - Drive the CS pin high, then low. - Hardware Reset (drive RESET pin low for at least 10 µs).
CS5463 5.16 Commands All commands are 8 bits in length. Any command byte value that is not listed in this section is invalid. Commands that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent which can execute during the original read). All commands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands. 5.16.
CS5463 5.16.5 Register Read/Write B7 0 B6 W/R B5 RA4 B4 RA3 B3 RA2 B2 RA1 B1 RA0 B0 0 The Read/Write informs the command decoder that a register access is required. During a read operation, the addressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK.
CS5463 Register Page 1 Address 0 1 2 3 RA[4:0] 00000 00001 00010 00011 Name PulseWidth LoadMin TGain Toff Description Energy Pulse Output Width No Load Threshold Temperature Sensor Gain Temperature Sensor Offset Name VSAGDuration VSAGLevel ISAGDuration ISAGLevel Description Voltage sag sample interval Voltage sag level Current fault sample interval Current fault level Register Page 3 Address 6 7 10 11 RA[4:0] 00110 00111 01010 01011 Note: For proper operation, do not attempt to write to unspecifie
CS5463 6. REGISTER DESCRIPTION 1. “Default” = bit status after power-on or reset 2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits. 6.1 Page 0 Registers 6.1.1 Configuration Register ( Config ) Address: 0 23 PC6 22 PC5 21 PC4 20 PC3 19 PC2 18 PC1 17 PC0 16 Igain 15 EWA 14 - 13 - 12 IMODE 11 IINV 10 - 9 - 8 - 7 - 6 - 5 - 4 iCPU 3 K3 2 K2 1 K1 0 K0 Default = 0x000001 26 PC[6:0] Phase compensation.
CS5463 6.1.2 Current and Voltage DC Offset Register ( IDCoff , VDCoff ) Address: 1 (Current DC Offset); 3 (Voltage DC Offset) MSB 0 -(2 ) LSB 2 -1 2 -2 -3 2 -4 2 -5 2 -6 2 -7 2 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 0x000000 The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the calibration.
CS5463 6.1.6 Instantaneous Current, Voltage, and Power Registers ( I , V , P ) Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power) MSB 0 -(2 ) LSB 2 -1 2 -2 -3 2 -4 2 -5 2 -6 2 -7 2 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous voltage and current samples are multiplied to obtain Instantaneous Power (P).
CS5463 6.1.10 Power Offset Register ( Poff ) Address: 14 MSB LSB 0 -(2 ) 2 -1 2 -2 -3 2 -4 -5 2 2 -6 -7 2 2 2-17 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Default = 0x000000 Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system.
CS5463 lates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the voltage channel’s differential input voltage (current) range. Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. LSD Low Supply Detect.
CS5463 IHPF (VHPF) Enables the high-pass filter on the current (voltage) channel. 0 = High-pass filter disabled (default) 1 = High-pass filter enabled Note: When either IHPF or VHPF are enabled, but not both, an all-pass filter is applied to the opposite channel for phase matching. IIR Enables the IIR compensation filters.
CS5463 6.1.17 Reactive Power Register ( QTrig ) Address: 24 MSB 0 LSB 2 -1 2 -2 -3 2 -4 2 -5 2 -6 2 -7 2 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 The Reactive Power (QTrig) is calculated using trigonometric identities. (See Section 4.3 Power Measurements on page 14). The value is represented in unsigned notation and in the range of 0 S 1.0, with the binary point to the right of the MSB. 6.1.
CS5463 6.1.20 Control Register ( Ctrl ) Register Address: 28 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 STOP 7 6 5 4 INTOD 3 2 NOCPU 1 NOOSC 0 Default = 0x000000 STOP Terminates the auto-boot sequence. 0 = Normal (default) 1 = Stop sequence INTOD Converts INT output pin to an open drain output. 0 = Normal (default) 1 = Open drain NOCPU Saves power by disabling the CPUCLK pin. 0 = Normal (default) 1 = Disables CPUCLK NOOSC Saves power by disabling the crystal oscillator.
CS5463 6.1.23 Fundamental Reactive Power Register ( QH ) Address: 31 (read only) MSB 0 -(2 ) LSB 2 -1 2 -2 -3 2 -4 2 -5 2 -6 2 -7 2 ..... 2-17 2 -18 2 -19 2 -20 2 -21 2 -22 2-23 Fundamental Reactive Power (QH) is calculated by performing a discrete Fourier transform (DFT) at the relevant frequency on the V and I channels. The value is represented in two's complement notation and in the range of -1.0 QH 1.0, with the binary point to the right of the MSB. 6.1.
CS5463 6.2 Page 1 Registers 6.2.1 Energy Pulse Output Width ( PulseWidth ) Address: 0 MSB LSB 222 0 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 1 PulseWidth sets the duration of energy pulses (tPW). The actual pulse duration is the contents of PulseWidth divided by the output word rate (OWR). PulseWidth is an integer in the range of 1 to 8388607. 6.2.2 No Load Threshold ( LoadMin ) Address: 1 MSB -(20) LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 .....
CS5463 6.3 Page 3 Registers 6.3.1 Voltage Sag and Current Fault Duration Registers ( VSAGDuration , ISAGDuration ) Address: 6 (Voltage Sag Duration); 10 (Current Fault Duration) MSB 0 LSB 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20 Default = 0x000000 Voltage Sag Duration (VSAGDuration) and Current Fault Duration (ISAGDuration) defines the number of instantaneous measurements utilized to determine a sag event. Setting these register to zero will disable this feature.
CS5463 7. SYSTEM CALIBRATION 7.1 Channel Offset and Gain Calibration The CS5463 provides digital DC offset and gain compensation that can be applied to the instantaneous voltage and current measurements, and AC offset compensation to the voltage and current RMS calculations. Since the voltage and current channels have independent offset and gain registers, system offset and/or gain can be performed on either channel without the calibration results from one channel affecting the other.
CS5463 each instantaneous measurement to nullify the DC component present in the system during conversion commands. A typical rms calibration value which allows for reasonable over-range margin would be 0.6 or 60% of the voltage and current channel’s maximum input voltage level. 7.1.2.2 AC Offset Calibration Sequence Two examples of AC gain calibration and the updated digital output codes of the channel’s instantaneous data registers are shown in Figures 15 and 16.
CS5463 However, an AC signal cannot be used for DC gain calibration. culated in step 2 by the gain calculated in step 3 and updating the AC offset register with the product. 7.1.3.2 DC Gain Calibration Sequence 7.2 Phase Compensation Initiate a DC gain calibration. The corresponding gain register is restored to default (1.0). The DC gain calibration averages the channel’s instantaneous measurements over one computation cycle (N samples). The average is then divided into 1.
CS5463 8. AUTO-BOOT MODE USING E2PROM When the CS5463 MODE pin is asserted (logic 1), the CS5463 auto-boot mode is enabled. In auto-boot mode, the CS5463 downloads the required commands and register data from an external serial E2PROM, allowing the CS5463 to begin performing energy measurements. 8.1 Auto-boot Configuration A typical auto-boot serial connection between the CS5463 and a E2PROM is illustrated in Figure 17. In auto-boot mode, the CS5463’s CS and SCLK are configured as outputs.
CS5463 9. BASIC APPLICATION CIRCUITS Figure 18 shows the CS5463 configured to measure power in a single-phase, 2-wire system while operating in a single-supply configuration. In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of shunt-resistor configuration, the common-mode level of the CS5463 must be referenced to the line side of the power line.
CS5463 10 k 5 k 120 VAC N L Voltage Transformer 200 10 200 0.1 µF 0.1µF 12 VAC 14 VA+ 200µF 12 VAC 3 VD+ CS5463 M:1 9 1k R V+ C Vdiff R V- 1k PFMON CPUCLK XOUT VIN+ 10 Low Phase-Shift Potential Transformer VIN- XIN R I- N:1 15 1k RESET 1k 16 RI+ 12 11 2 1 4.096 MHz Optional Clock Source 24 19 7 CS 23 SDI 6 SDO 5 SCLK 20 INT C Idiff RBurden Current Transformer IIN- 17 IIN+ VREFIN VREFOUT E2 E1 0.
CS5463 5 k 10 k 240 VAC L1 L2 500 1 k 10 470 µF 235 nF 0.1 µF 0.1 µF 3 VD+ 14 VA+ CS5463 9 CV+ R2 CI+ R V- CVdiff 10 16 1k 17 PFMON 2 CPUCLK 1 XOUT VINIIN+ XIN 4.096 MHz Optional Clock Source 24 R I+ RBurden CIdiff 1k 15 R I- IIN- 12 VREFIN 11 VREFOUT RESET 19 CS SDI SDO SCLK 7 23 6 5 INT E2 E1 0.1 µF AGND 13 Note: Indicates common (floating) return. ISOLATION R1 VIN+ Serial Data Interface 20 22 21 DGND 4 Mech. Counter or Stepper Motor Figure 21.
CS5463 10.PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING N D E11 A2 E A e b2 SIDE VIEW A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.068 -0.323 0.307 0.209 0.026 0.03 4° MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.13 1.73 -8.20 7.80 5.30 0.65 0.75 4° NOTE MAX 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.
CS5463 11. ORDERING INFORMATION Model CS5463-ISZ (lead free) Temperature Package -40 to +85 °C 24-pin SSOP 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5463-ISZ (lead free) Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
CS5463 13. REVISION HISTORY Revision Date Changes A1 MAR 2005 Advance Release PP1 AUG 2005 First preliminary release. F1 NOV 2005 First final release, updated with most-current characterization data. F2 APR 2008 Added PulseWidth & LoadMin Registers. F3 APR 2011 Removed lead-containing (Pb) device ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.
