Owner's manual

CS5451A
10 DS635F4
When data is not being transferred SCLK is held low.
(see Figure 3.)
The framing signal (FSO) output is normally low. FSO
goes high, with a pulse width equal to one SCLK period,
when the instantaneous voltage and current data sam-
ples are about to be transmitted out of the serial inter-
face (after each A/D conversion cycle). SCLK is not
active during FSO high.
For 96 SCLK periods after FSO falls, SCLK is active and
SDO provides valid output. Six channels of 16-bit data
are output, MSB first. Figure 4
illustrates how the volt-
age and current measurements are output for the three
phases. SCLK will then be held low until the next sam-
ple period.
4.5 System Initialization
A hardware reset is initiated when the RESET pin is
forced low with a minimum pulse width of 50 ns. When
RESET
is activated, all internal registers are set to a de-
fault state.
Upon powering up, the RESET
pin must be held low
(active) until after the power stabilizes.
4.6 Voltage Reference
The CS5451A is specified for operation with a +1.2 V
reference between the VREFIN and AGND pins. The
converter includes an internal 1.2 V reference that can
be used by connecting the VREFOUT pin to the VRE-
FIN pin of the device. The VREFIN can be used to con-
nect external filtering and/or references.
4.7 Power Supply
The low, stable analog power consumption and superior
supply rejection of the CS5451A allow for the use of a
simple charge-pump negative supply generator. The
use of a negative supply alleviates the need for level
SCLK
FSO
SDO
1215
14
13
0123456789
1011
15
14
13 12 11 10 9 8 7
65
4321
Channel 1 ( I )
Channel 1 ( V )
01514
. . .
Ch. 2 ( V ) Ch. 2 ( I )
Ch. 3 ( V ) Ch. 3 ( I )
... ... ...
. . .
. . .
. . .
[ Low ]
[ Low ]
. . .
. . .
. . .
012
3
96 SCLKs
Figure 3. One Data Frame
SCLK
FSO
SDO
Channel 1 V
Channel 2 I
Channel 3 I
Channel 2 V
Channel 3 V
Channel 1 I
Each data segment
is 16 bits long.
96 SCLKs
Figure 4. Serial Port Data Transfer