User Manual

6 DS992F1
CS53L30
1.3 Pin Descriptions
MIC_BIAS_FILT D6 15 VP I Microphone Bias Voltage Filter. Filter
connection for the internal quiescent
voltage used for the MICx_BIAS outputs.
————
FILT+ A6 9 VA O Positive Reference Filter. Positive
reference voltage filter for internal
sampling circuits.
————
MIC1_BIAS
MIC2_BIAS
MIC3_BIAS
MIC4_BIAS
C4
C5
C6
D5
11
12
13
14
VP O Microphone Bias Voltage. Low-noise
bias supply for an external mic.
———Hi-Z
INT
—17 VA OInterrupt. Outgoing interrupt signal
generated upon registering an error
(fault).
—CMOS
open-drain
output
—Hi-Z
RESET
E5 18 VA I Reset. The device enters a low power
mode when this pin is driven low.
— — Hysteresis
on CMOS
input
—
SYNC D4 19 VA I/O Multidevice Synchronization Signal.
Synchronization output when SYNC_EN
is set, otherwise it is a synchronization
input. Defaults to input.
Weak
pulldown
CMOS
output
Hysteresis
on CMOS
input
Hi-Z
SCL D3 24 VA I Serial Control Port Clock. Serial clock
for the I
2
C port.
— — Hysteresis
on CMOS
input
—
SDA E2 25 VA I/O Serial Control Data. Bidirectional data
pin for the I
2
C port.
—CMOS
open-drain
output
Hysteresis
on CMOS
input
—
MCLK E1 26 VA I Master Clock. Clock source for device’s
core.
Weak
pulldown
— Hysteresis
on CMOS
input
—
ASP_SCLK D2 27 VA I/O Audio Serial Clock. Audio bit clock. Input
in Slave Mode, output in Master Mode.
Weak
pulldown
CMOS
output
Hysteresis
on CMOS
input
Hi-Z
ASP_LRCK/
FSYNC
C3 22 VA I/O Audio Left/Right Clock/Frame SYNC.
Identifies the start of each serialized PCM
data word and indicates the active
channel on each serial PCM audio data
line. Input in Slave Mode, output in Master
Mode.
Weak
pulldown
CMOS
output
Hysteresis
on CMOS
input
Hi-Z
ASP_SDOUT1 D1 28 VA O Audio Data Output. Output for the two’s
complement serial PCM data. Channels 1
and 2 are output in I
2
S Mode, while all four
channels of data are output on this single
pin in TDM Mode.
Weak
pulldown
Tristateable
CMOS
output
—Hi-Z
ASP_SDOUT2/
AD0
E3 23 VA I/O Audio Data Output/Address Select.
Output for the two’s-complement serial
PCM data. Channels 3 and 4 are output in
I
2
S Mode. Along with DMIC2_SCLK/AD1,
immediately sets the I
2
C address when
RESET
is deasserted. Default is 0.
Weak
pulldown
Tristateable
CMOS
output
—Hi-Z
DMIC1_SCLK C2 29 VA O Digital MIC Interface 1 Serial Clock.
High speed clock output to the digital
mics.
Weak
pulldown
CMOS
output
—Hi-Z
Table 1-1. Pin Descriptions (Cont.)
Name
Ball
#
Pin
#
Power
Supply
I/O Description
Internal
Connection
Driver Receiver
State at
Reset
Filter pins
Analog Outputs
Digital I/O