User Manual

DS992F1 5
CS53L30
1.2 QFN
1.2 QFN
Figure 1-2. Top-Down (Through-Package) View—32-Pin QFN Package
1.3 Pin Descriptions
Table 1-1. Pin Descriptions
Name
Ball
#
Pin
#
Power
Supply
I/O Description
Internal
Connection
Driver Receiver
State at
Reset
IN1+/DMIC1_SD
IN2+
IN3+/DMIC2_SD
IN4+
A1
A2
A3
A4
31
1
3
5
VA I Noninverting Inputs/DMIC Inputs.
Positive analog inputs for the stereo
ADCs when CH_TYPE = 0 (default) or
DMIC inputs when CH_TYPE = 1.
Programmable — Hysteresis
on CMOS
input
—
IN1–
IN2–
IN3–
IN4–
B1
B2
B3
B4
32
2
4
6
VA I Inverting Inputs. Negative analog inputs
for the stereo ADCs when CH_TYPE = 0
(default) or unused when CH_TYPE = 1.
Programmable — Hysteresis
on CMOS
input
—
Thermal Pad
109
8
7
6
5
4
3
2
1
11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
SCL
ASP_SDOUT2/AD0
ASP_LRCK/FSYNC
VA
GNDD
SYNC
RESET
INTGNDA
MUTE
IN1–
DMIC2_SCLK/AD1 IN1+/DMIC1_SD DMIC1_SCLK ASP_SDOUT1 ASP_SCLK MCLK SDA
MIC_BIAS_FILT
MIC4_BIAS MIC3_BIAS MIC2_BIAS MIC1_BIAS
VP
FILT+
VA
IN4–
IN4+
IN3–
IN3+/DMIC2_SD
IN2–
IN2+
Capture-Path Pins