User Manual

48 DS992F1
CS53L30
7.6 MCLK Control
5 DISCHARGE_
FILT+
Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this bit, ensure that the
VA pin is connected to a supply, as described in Table 3-1.
0 (Default) FILT+ is not clamped to ground.
1 FILT+ is clamped to ground. This must be set only if PDN_ULP or PDN_LP = 1. Discharge time with an external
2.2-µF capacitor on FILT+ is ~46 ms.
4 THMS_PDN Thermal-sense power down. Configures the state of the power sense circuit.
0 Powered up.
1 (Default) Powered down.
3:0 — Reserved
7.6 MCLK Control
Address 0x07
R/W
7 6 543210
MCLK_DIS MCLK_INT_SCALE DMIC_DRIVE — MCLK_DIV[1:0] SYNC_EN —
Default0 0 000100
Bits Name Description
7 MCLK_DIS Master clock disable. Configures the state of the internal MCLK signal prior to its fanout to all internal circuitry.
0 (Default) On
1 Off; Disables the clock tree to save power when the device is powered down and the external MCLK is running.
Note: The external MCLK must be running whenever this bit is altered.
6MCLK_INT_
SCALE
Internal MCLK scaling enable. Allows internal modulator rate to be scaled with the ASP_RATE setting to save power.
0 (Default) Off. MCLK
INT
and Fs
INT
divide-ratio is 1.
1 On. Enables internal MCLK and Fs
INT
scaling. MCLK
INT
and Fs
INT
divide ratio is either 2 or 4, depending on ASP_
RATE and INTERNAL_FS_RATIO settings (see Table 4-2).
5DMIC_
DRIVE
DMIC clock output drive strength. Selects the drive strength used for the DMICx clock outputs. Table 3-14 describes
drive-strength specifications.
0 (Default) Normal
1 Decreased
4—Reserved
3:2 MCLK_DIV Master clock divide ratio. Selects the divide ratio between the selected MCLK source and the internal MCLK (MCLK
INT
).
Table 4-2 lists supported MCLK rates and their associated programming settings.
00 Divide by 1
01 (Default) Divide by 2
10 Divide by 3
11 Reserved
• This field must be changed only if PDN_ULP or PDN_LP = 1 and MCLK_DIS = 1.
• The control port’s autoincrement feature is not supported on this bit field.
1 SYNC_EN Multichip synchronization enable. Toggle high to enable synchronization sequence.
0)(Default) No activity
1)Begins multichip synchronization sequence. To restart the sequence this bit must be cleared and then set.
0—Reserved
7.7 Internal Sample Rate Control
Address 0x08
R/W
765 4 321 0
— INTERNAL_FS_RATIO — MCLK_19MHZ_EN
Default 0 0 0 1 1 1 0 0
Bits Name Description
7:5 — Reserved
4 INTERNAL_
FS_RATIO
Internal sample rate (Fs
int
). Selects the divide ratio from MCLK
INT
to produce the internal sample rate used for all
converters. Slave/Master Mode is determined by ASP_M/S on p. 49.
0MCLK
INT
/125
1 (Default) MCLK
INT
/128
3:1 — Reserved
0MCLK_
19MHZ_EN
19.2-MHz MCLK enable. (Slave/Master Mode is determined by ASP_M/S on p. 49.)
0 (Default) MCLK
19.2 MHz
1MCLK
= 19.2 MHz
Bits Name Description