User Manual

42 DS992F1
CS53L30
5.4 Capture-Path Inputs
5.4 Capture-Path Inputs
The CS53L30 capture-path inputs can accept either analog or digital sources. This section describes the capture-path pins
signal amplitude limitations.
5.4.1 Maximum Input Signal Level
Clipping mechanisms in the capture-path must be identified to quantify the maximum input signal level. The CS53L30
offers two such mechanisms:
• Clipping occurs if the input signal level exceeds the input pin-protection-diode turn-on voltage, as described in
Section 5.4.1.1.
• Clipping occurs if ADC full-scale input level is exceeded, as described in Section 5.4.1.2.
5.4.1.1 Capture-Path Pin-Protection Diodes
The capture-path pins are specified with an absolute maximum rating (Table 3-2) that should not be exceeded; that is, the
voltage at the IN± pins should not be higher than VA + 0.3 V or lower than GNDA – 0.3 V. The 0.3-V offsets from VA and
GNDA are derived from the threshold voltage of the protection diodes used for voltage clamping at the capture-path pins.
Fig. 5-2 and Fig. 5-3 show the voltage relationship between a differential analog input signal and the absolute maximum
rating of the capture-path pins.
3 Write the following
registers to power down
the device.
REGISTER/BIT FIELDS VALUE DESCRIPTION
Power Control, Address 0x06 0x90
PDN_ULP
PDN_LP
DISCHARGE_FILT+
THMS_PDN
Reserved
1
0
0
1
0000
Ultralow power down is enabled.
Power down is not enabled.
FILT+ pin is not clamped to ground.
Thermal sense is powered down.
—
4 Poll the interrupt status
register until the PDN_
DONE status bit is set.
REGISTER/BIT FIELDS VALUE DESCRIPTION
Device Interrupt Status, Address 0x36
PDN_DONE
THMS_TRIP
SYNC_DONE
ADC2B_OVFL
ADC2A_OVFL
ADC1B_OVFL
ADC1A_OVFL
MUTE_PIN
1
x
x
x
x
x
x
x
Device has completely powered down.
Indicates thermal sense trip.
Indicates multichip synchronization sequence done.
Indicates overrange status in corresponding signal path.
Indicates overrange status in corresponding signal path.
Indicates overrange status in corresponding signal path.
Indicates overrange status in corresponding signal path.
Indicates MUTE pin assertion.
5 (Optional) Discharge the
FILT+ capacitor.
REGISTER/BIT FIELDS VALUE DESCRIPTION
Power Control, Address 0x06 0xB0
PDN_ULP
PDN_LP
DISCHARGE_FILT+
THMS_PDN
Reserved
1
0
1
1
0000
Ultralow power down is enabled.
Power down is not enabled.
FILT+ pin is clamped to ground.
Thermal sense is powered down.
—
6 (Optional) Remove MCLK.
7
(Optional) Assert reset by driving the R
ESET pin low.
8 (Optional) Remove power first from VA, then from VP.
Example 5-2. Power-Down Sequence (Cont.)
STEP TASK