User Manual

DS992F1 31
CS53L30
4.7 TDM Mode
4.7.2 Bursted SCLK
After all the data is sent on the TDM bus, it is not necessary to continue to toggle SCLK for the remaining unused slots.
Not toggling SCLK after all data is sent and received saves power, by avoiding driving the output and clock capacitances
unnecessarily. When the device is operating as a timing slave, bursted SCLK is naturally supported, since data is clocked
out only when SCLK toggles. When the device is operating as a timing master, bursted SCLK is not supported.
6.0000 8.000 48 366
11.025 48 160
12.000 48 116
16.000 46 7
22.050 34 0
24.000 31 2
32.000 23 4
44.100 17 0
48.000 15 5
12.0000 8.000 48 1116
11.025 48 704
12.000 48 616
16.000 48 366
22.050 48 160
24.000 48 116
32.000 46 8
44.100 34 0
48.000 31 2
6.1440 8.000 48 384
11.025 48 173
12.000 48 128
16.000 48 0
22.050 34 6
24.000 32 0
32.000 24 0
44.100 17 3
48.000 16 0
12.2880 8.000 48 1152
11.025 48 731
12.000 48 640
16.000 48 384
22.050 48 173
24.000 48 128
32.000 48 0
44.100 34 6
48.000 32 0
6.4000
1
8.000 48 416
11.025 48 196
12.000 48 149
16.000 48 16
22.050 36 2
24.000 33 2
32.000 25 0
44.100 18 1
48.000 16 5
1. 6.4 MHz is the highest SCLK frequency allowed if MCLK_19MHZ_EN is set.
Table 4-3. Slot Count and Resulting Unused Clock Cycles for Supported SCLK and Sample Rates (Cont.)
SCLK Frequency [MHz] FSYNC Sample Rate [kHz] Number of Available Slots Resulting Number of Unused SCLK Cycles