Owner manual

6 DS700PP1
CS53L21
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
Pin Name # Pin Description
LRCK
1
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDA/CDIN
(MCLKDIV2)
2
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
SCL/CCLK
(I²S/LJ)
3
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-
mats for the ADC.
AD0/CS
(TSTN)
4
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-select signal for SPI format.
Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to
DGND for normal operation.
VA_PULLUP
5
Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA
using a 47 kΩ resistor.
TSTO
6
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
AGND
7
Analog Ground (Input) - Ground reference for the internal analog section.
TSTO
8
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
109
8
7
6
5
4
3
2
1
11
12
13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
CS53L21
VD
DGND
SDOUT (M/S
)
MCLK
TSTN
SCLK
TSTO
NIC
NIC
VA
AGND
TSTO
FILT+
VQ
SDA/CDIN (MCLKDIV2)
SCL/CCLK (I²S/LJ
)
AD0/CS
(TSTN)
TSTO
VL
RESET
AGND
TSTO
AFILTA
AIN1A
AIN1B
AIN2A
AIN2B/BIAS
MICIN1/AIN3A
MICIN2/BIAS/AIN3B
AFILTB
VA_PULLUP
LRCK