Owner manual

DS700PP1 31

CS53L21

4.5.3 High-Impedance Digital Output

The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-

out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-

ance state, allowing another device to transmit serial port data without bus contention..

4.5.4 Quarter- and Half-Speed Mode

Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a

relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow

lower frequency sample rates.

4.6 Digital Interface Formats

The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit depths from

16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK. Figures 15-16 illustrate

the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 14 for exact

timing relationship between clocks and data.

Software

Control:

“Interface Control (Address 04h)” on page 43.

Hardware

Control:

Pin Setting Selection

“I²S/LJ” pin 3

Left-Justified Interface

I²S Interface

CS53L21

Transmitting Device #1

Transmitting Device #2

Receiving Device

3ST_SP

SDOUT

SCLK/LRCK

Figure 14. Tri-State Serial Port

LRCK

SCLK

MSB LSB

MSB

LSB

AOUTA / AINxA

Left Channel Right Channel

SDIN

AOUTB / AINxB

MSB

Figure 15. I²S Format