Owner manual

14 DS700PP1
CS53L21
ADC DIGITAL FILTER CHARACTERISTICS
6. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 23 to 26) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters
are for Fs = 48 kHz.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C
LOAD
= 15 pF.)
Parameter (Note 6) Min Typ Max Unit
Passband (Frequency Response) to -0.1 dB corner
0 - 0.4948 Fs
Passband Ripple
-0.09 - 0.17 dB
Stopband
0.6 - - Fs
Stopband Attenuation
33 - - dB
Total Group Delay
- 7.6/Fs - s
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB
-0.13 dB
-
-
3.7
24.2
-
-
Hz
Hz
Phase Deviation @ 20 Hz
-10-Deg
Passband Ripple
- - 0.17 dB
Filter Settling Time
-10
5
/Fs 0 s
Parameters Symbol Min Max Units
RESET
pin Low Pulse Width (Note 7)
1-ms
MCLK Frequency
1.024 38.4 MHz
MCLK Duty Cycle (Note 8)
45 55 %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
F
s
F
s
F
s
F
s
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
LRCK Duty Cycle
45 55 %
SCLK Frequency
1/t
P
-64•F
s
Hz
SCLK Duty Cycle
45 55 %
LRCK Setup Time Before SCLK Rising Edge
t
s(LK-SK)
40 - ns
LRCK Edge to SDOUT MSB Output Delay
t
d(MSB)
-52ns
SDOUT Setup Time Before SCLK Rising Edge
t
s(SDO-SK)
20 - ns
SDOUT Hold Time After SCLK Rising Edge
t
h(SK-SDO)
30 - ns