CS53L21 Low Power, Stereo Analog to Digital Converter FEATURES SYSTEM FEATURES 98 dB Dynamic Range (A-wtd) 24-bit Conversion -88 dB THD+N 4 kHz to 96 kHz Sample Rate Analog Gain Controls – +32 dB or +16 dB MIC Pre-Amplifiers Multi-bit Delta Sigma Architecture – Analog Programmable Gain Amplifier (PGA) Low Power Operation +20 dB Digital Boost – Stereo Record (ADC): 8.72 mW @ 1.8 V – Stereo Record (MIC to PGA and ADC): 13.73 mW @ 1.
CS53L21 APPLICATIONS GENERAL DESCRIPTION Portable Audio Players The CS53L21 is a highly integrated, 24-bit, 96 kHz, low power stereo A/D. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many features suitable for low power, portable system applications.
CS53L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ................................................
CS53L21 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 40 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................................... 41 6.4 Interface Control (Address 04h) ...............................................................................
CS53L21 Figure 21.AIN & PGA Selection ................................................................................................................ 47 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56 Figure 23.ADC Passband Ripple .............................................................................................................. 60 Figure 24.ADC Stopband Rejection .....................................................
CS53L21 Pin Name # LRCK 1 SDA/CDIN (MCLKDIV2) 2 SCL/CCLK (I²S/LJ) 3 TSTN SCLK MCLK SDOUT (M/S) DGND VD VL RESET 1.
CS53L21 TSTO 9 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no connection external to the pin). NIC NIC 10 11 .Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left “floating”. No other external connection should be made to this pin. VA 12 Analog Power (Input) - Positive power for the internal analog section.
CS53L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) I/O Driver Receiver RESET Input - 1.8 V - 3.3 V SCL/CCLK (I²S/LJ) Input - 1.8 V - 3.3 V, with Hysteresis SDA/CDIN (MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis AD0/CS (DEM) Input - 1.8 V - 3.3 V MCLK Input - 1.8 V - 3.3 V LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.
CS53L21 2. TYPICAL CONNECTION DIAGRAMS See Note 4 +1.8 V or +2.5 V 1 µF 0.1 µF 0.1 µF Note 4: Series resistance in the path of the power supplies must be avoided. 47 kΩ VD +1.8 V or +2.
CS53L21 See Note 4 +1.8V or +2.5V 1 µF 0.1 µF 0.1 µF +1.8V or +2.5V 47 kΩ VD VA Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. VA_ PULLUP CS53L21 TSTN MCLK SCLK LRCK AIN1A VL or DGND (1) SDOUT/ M/S Digital Audio Processor Left Analog Input 1 1800 pF * 1 µF 100 Ω 100 kΩ 1800 pF * 100 kΩ 100 Ω AIN1B Right Analog Input 1 1 µF RESET I²S/LJ FILT+ MCLKDIV2 10 µF AGND * +1.8V, 2.5 V or +3.3V AFILTA AFILTB VQ VL 0.
CS53L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters Symbol Min Nom Max Units 1.65 2.37 1.65 2.37 1.65 2.37 3.14 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.
CS53L21 ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max Parameter (Note 4) VA = 1.
CS53L21 ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test Conditions (unless otherwise specified): Input sine wave (relative to full scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz) VA = 2.5 V (nominal) Min Typ Max Parameter (Note 4) VA = 1.
CS53L21 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 6) Min Typ Max Unit 0 - 0.4948 Fs -0.09 - 0.17 dB Stopband 0.6 - - Fs Stopband Attenuation 33 - - dB - 7.6/Fs - s Passband (Frequency Response) to -0.1 dB corner Passband Ripple Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) Frequency Response -3.0 dB -0.13 dB - 3.7 24.2 - Hz Hz Phase Deviation @ 20 Hz - 10 - Deg - - 0.17 dB - 5 0 s Passband Ripple Filter Settling Time 10 /Fs 6.
CS53L21 Parameters Symbol Min Fs - Max Units Master Mode (Note 9) Output Sample Rate (LRCK) All Speed Modes (Note 10) MCLK ----------------128 Hz 45 55 % - 64•Fs Hz 45 55 % td(MSB) - 52 ns SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns LRCK Duty Cycle 1/tP SCLK Frequency SCLK Duty Cycle LRCK Edge to SDOUT MSB Output Delay 7.
CS53L21 SWITCHING SPECIFICATIONS - I²C CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
CS53L21 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RESET Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.
CS53L21 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Min Typ Max Units Nominal Voltage Output Impedance DC Current Source/Sink (Note 14) - 0.5•VA 23 - 10 V kΩ μA FILT+ - VA - V 0.8•VA 0.7•VA 0.6•VA 0.
CS53L21 POWER CONSUMPTION See (Note 17) Reserved bit 6 Reserved bit 5 PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN PDN_MICB PDN_MICA PDN_MICBIAS Power Ctl. Registers 02h 03h Operation Typical Current (mA) iVA iVD iVL (Note 20) V Total Power (mWrms) 1 Off (Note 18) x x x x x x x x x x 1.8 2.5 0 0 0 0 0 0 0 0 2 Standby (Note 19) x x x x x x 1 x x x 1.8 2.5 0.01 0.02 0 0.05 0.01 0.03 0 0.10 3 Mono Record ADC 1 1 1 1 1 0 0 1 1 1 1.8 2.5 PGA to ADC 1 1 1 0 1 0 0 1 1 1 1.8 1.85 2.
CS53L21 4. APPLICATIONS 4.1 4.1.1 Overview Architecture The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK). 4.1.
CS53L21 4.2 Hardware Mode A limited feature-set is available when the A/D powers up in Hardware Mode (see “Recommended PowerUp Sequence” on page 32) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available.
CS53L21 4.3 Analog Inputs AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel.
CS53L21 4.3.2 High-Pass Filter and DC Offset Calibration The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1.
CS53L21 1 fc = ----------------------------------------------- = 3.18 Hz 2π ( 50 kΩ ) ( 1 μF ) The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. The MICBIAS output pin is selected using the MICBIAS_SEL bit. Software Controls: “Interface Control (Address 04h)” on page 43, “MIC Control (Address 05h)” on page 44. MICBIAS 20 MICIN1 + // 17 Σ + // MICIN2 18 Figure 8. MIC Input Mix w/Common Mode Rejection 2.5 V 2.15 V VA AINxA 1.25 V 0.
CS53L21 4.3.5 Analog Input Multiplexer A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up.
CS53L21 4.3.7 Automatic Level Control (ALC) When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold.
CS53L21 4.3.8 Noise Gate The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before the noise gate attacks the signal. Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC pre-amplifier.
CS53L21 4.4 Signal Processing Engine The SPE provides various signal processing functions that apply to the ADC data. Software Controls: “SPE Control (Address 09h)” on page 48 INPUTS FROM ADCA and ADCB SIGNAL PROCESSING ENGINE (SPE) MUTE_ADCMIXA MUTE_ADCMIXB ADCMIXA_VOL[6:0] ADCMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps VOL ADCA[1:0] ADCB[1:0] Channel Swap Digital Mix to ADC Serial Interface Figure 12. Signal Processing Engine 4.4.
CS53L21 4.5 Serial Port Clocking The A/D serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device.
CS53L21 4.5.1 Slave LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits.
CS53L21 4.5.3 High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-impedance state, allowing another device to transmit serial port data without bus contention.. CS53L21 Transmitting Device #2 Transmitting Device #1 SDOUT 3ST_SP SCLK/LRCK Receiving Device Figure 14. Tri-State Serial Port 4.5.
CS53L21 LRCK L eft C h a n n e l R ig ht C h a n n el SCLK SDIN MSB LSB M SB LSB MSB AOUTB / AINxB AOUTA / AINxA Figure 16. Left-Justified Format 4.7 Initialization The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 33. The A/D enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset.
CS53L21 4.9 Recommended Power-Down Sequence To minimize audible pops when turning off or placing the A/D in standby, 1. Mute the ADC’s. 2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until it reaches a fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. Bring RESET low. No Power 1. No audio signal generated.
CS53L21 4.10 Software Mode The control port is used to access the registers allowing the A/D to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in two modes: SPI and I²C, with the A/D acting as a slave device.
CS53L21 increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to the CS53L21 from the microcontroller after each transmitted byte.
CS53L21 4.10.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.10.3.1 Map Increment (INCR) The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes.
CS53L21 5. REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state. Addr 01h Function ID p 40 default 02h Power Ctl. 1 p 40 default 03h Speed Ctl. & Power Ctl. 2 p 41 default 04h Interface Ctl. p 43 default 05h MIC Control & Misc.
CS53L21 Addr Function p 50 default 0Eh Vol. Control ADCMIXA p 51 default 0Fh Vol.
CS53L21 Addr 7 6 1Dh ALC Release Rate Reserved Reserved p 52 default 0 0 1 1 1 1 1 1 MAX2 MAX1 MAX0 MIN2 MIN1 MIN0 Reserved Reserved 0 0 0 0 0 0 0 0 NG_ALL NG_EN NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0 p 54 default 0 0 0 0 0 0 0 0 Status Reserved SP_CLK ERR p 55 default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 0 1Eh Function ALC Threshold p 53 default 1Fh 20
CS53L21 6. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All “Reserved” registers must maintain their default state. 6.1 Chip I.D.
CS53L21 Power Down PGA X (PDN_PGAX) Default: 0 0 - Disable 1 - Enable Function: PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control 1 (Address 02h) Note 1 above. This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to “ADCX Input Select Bits (AINX_MUX[1:0])” on page 47 for the required settings.
CS53L21 Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the A/D in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate.
CS53L21 6.4 Interface Control (Address 04h) 7 Reserved 6 M/S 5 Reserved 4 Reserved 3 Reserved 2 ADC_I²S/LJ 1 DIGMIX 0 MICMIX Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port.
CS53L21 ADC I²S or Left-Justified (ADC_I²S/LJ) Default: 0 0 - Left-Justified 1 - I²S Function: Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in this section “Digital Interface Formats” on page 31.
CS53L21 ADCx 20 dB Digital Boost (ADCx_DBOOST) Default: 0 0 - Disabled 1 - Enabled Function: Applies a 20 dB digital gain to the input signal on ADC channel x, regardless of the input path. MIC Bias Select (MICBIAS_SEL) Default: 0 0 - MICBIAS on AIN3B/MICIN2 pin 1 - MICBIAS on AIN2B pin Function: Determines the output pin for the internally generated MICBIAS signal. If set to ‘0’b, the MICBIAS is output on the AIN3B/MICIN2 pin. If set to ‘1’b, the MICBIAS is output on the AIN2B pin.
CS53L21 ADCX High-Pass Filter Freeze (ADCX_HPFRZ) Default: 0 0 - Continuous DC Subtraction 1 - Frozen DC Subtraction Function: The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC offset is frozen, and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to ‘1’.
CS53L21 6.7 ADCx Input Select, Invert & Mute (Address 07h) 7 AINB_MUX1 6 AINB_MUX0 5 AINA_MUX1 4 AINA_MUX0 3 INV_ADCB 2 INV_ADCA 1 0 ADCB_MUTE ADCA_MUTE ADCX Input Select Bits (AINX_MUX[1:0]) Default: 00 PDN_PGAx AINx_MUX[1:0] 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 Selected Path to ADC AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx AIN1x AIN2x AIN3x/MICINx Reserved Function: Selects the specified analog input signal into ADCx.
CS53L21 6.8 SPE Control (Address 09h) 7 Reserved 6 SPE_ENABLE 5 FREEZE 4 Reserved 3 Reserved 2 Reserved 1 SPE_SZC1 0 SPE_SZC0 SPE_ENABLE Default: 0 0 - Reserved 1 - ADC Serial Port to SPE Function: Selects the digital signal source for the SPE. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional.
CS53L21 SPE Soft Ramp and Zero Cross Control (SPE_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step.
CS53L21 ALCX Zero Cross Disable (ALCX_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the zero cross setting. ALC volume-level changes will take effect immediately in one step. PGA X Gain Control (PGAX_VOL[4:0]) Default: 00000 Binary Code Volume Setting 11000 ··· 01010 ··· 00000 11111 11110 ··· 11001 11010 +12 dB ··· +5 dB ··· 0 dB -0.
CS53L21 Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table above. Note: 6.11 When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually.
CS53L21 ADCA[1:0] 01 10 11 SDOUT ADCB[1:0] 01 L+R -----------2 10 R SDOUT L+R -----------2 11 L Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. 6.13 ALC Enable & Attack Rate (Address 1Ch) 7 ALC_ENB 6 ALC_ENA 5 4 3 2 1 0 ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0 ALC Enable (ALC_ENX) Default: 0 0 - Disabled 1 - Enabled Function: Enables automatic level control for ADC channel x.
CS53L21 Function: Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting. The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled. 6.
CS53L21 6.16 Noise Gate Configuration & Misc. (Address 1Fh) 7 NG_ALL 6 NG_EN 5 NG_BOOST 4 THRESH2 3 THRESH1 2 THRESH0 1 NGDELAY1 0 NGDELAY0 Noise Gate Channel Gang (NG_ALL) Default: 0 0 - Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect. Noise Gate Enable (NG_EN) Default: 0 0 - Disabled 1 - Enabled Function: Enables the noise gate.
CS53L21 6.17 Status (Address 20h) (Read Only) 7 Reserved 6 SP_CLKERR 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 ADCA_OVFL 0 ADCB_OVFL For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A ”0” means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0.
CS53L21 7. ANALOG PERFORMANCE PLOTS 7.1 ADC_FILT+ Capacitor Effects on THD+N The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 22 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB53L21 using an Audio Precision analyzer.
CS53L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 1024x MCLK (MHz) 1536x 2048x* 8 11.025 12 3072x* 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 512x 768x 16 22.05 24 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 256x 384x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 128x 192x 64 88.2 96 8.1920 11.2896 12.2880 12.2880 16.9344 18.
CS53L21 8.2 58 Auto Detect Disabled Sample Rate LRCK (kHz) 512x 8 11.025 12 6.1440 768x MCLK (MHz) 1024x 1536x 2048x 3072x 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 256x 384x 512x 16 22.05 24 6.1440 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 Sample Rate LRCK (kHz) 256x 32 44.1 48 8.1920 11.2896 12.2880 Sample Rate LRCK (kHz) 128x 64 88.2 96 8.1920 11.2896 12.2880 12.2880 16.9344 18.
CS53L21 9. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS53L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead.
CS53L21 10.DIGITAL FILTERS 60 Figure 23. ADC Passband Ripple Figure 24. ADC Stopband Rejection Figure 25. ADC Transition Band Figure 26.
CS53L21 11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
CS53L21 12.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING e b D Pin #1 Corner Pin #1 Corner E2 E A1 L D2 A Top View DIM MIN A A1 b D D2 E E2 e L -0.0000 0.0071 0.1280 0.1280 0.0118 Bottom View Side View INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157 MAX MIN 0.0394 0.0020 0.0110 -0.00 0.18 0.1319 3.25 0.1319 3.25 0.0197 0.30 MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40 NOTE MAX 1.00 0.05 0.28 3.35 3.35 0.
CS53L21 13.ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Commercial -10 to +70° C CS53L21 CDB53L21 Low-Power Stereo A/D CS53L21 Evaluation Board 32L-QFN - Yes No Automotive -40 to +85° C - - Container Order # Rail CS53L21-CNZ Tape & Reel CS53L21-CNZR Rail CS53L21-DNZ Tape & Reel CS53L21-DNZR - CDB53L21 14.REFERENCES 1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2.
CS53L21 15.REVISION HISTORY Revision A1 PP1 64 Changes Initial Release Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 11. Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Characteristics (Commercial - CNZ)” on page 12. Corrected Interchannel Gain Mismatch specification in “Analog Characteristics (Commercial - CNZ)” on page 12 and “Analog Characteristics (Automotive - DNZ)” on page 13.
CS53L21 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable.
CS53L21 66 DS700PP1
