Manual

CS5378
DS639F3 67
20.1.1 SPICTRL : 0x00, 0x01, 0x02
(MSB) 23 22 21 20 19 18 17 16
-- -- -- -- -- -- -- --
R/W R/W1 R/W R/W R/W R/W R/W R/W
00001011
15 14 13 12 11 10 9 8
SMODF----EMOPSWEF----E2DREQ
R R/W R R R R/W R/W R/W
00000010
7654321(LSB) 0
-- -- -- -- -- -- -- --
R/WR/WR/WR/WR/WR/WR/WR/W
00100000
SPI Address: 0x00
0x01
0x02
-- Not defined;
read as 0
RReadable
WWritable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 -- reserved 15 SMODF SPI mode fault flag 7:0 -- reserved
14:13 -- reserved
12 EMOP External master to SPI
operation in progress
flag
11 SWEF SPI write collision error
flag
10:9 -- reserved
8 E2DREQ External master to digital
filter request flag
Figure 39. SPI Control Register SPICTRL