Instruction Manual

CS5374

9.3 AMP2CFG: 0x02

(MSB)7654321(LSB)0

PWDN2 HP2 MUX2_1 MUX2_0 --- GAIN2_2 GAIN2_1 GAIN2_0

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

Figure 22. Amplifier 2 Configuration Register AMP2CFG

Bit definitions:

7 PWDN2 Amplifier 2 Power Down

1: enable

0: disable

6 HP2 Amplifier 2 High Precision

1: enable

0: disable

5:4 MUX2[1:0] Input Multiplexer

11: INA2 + INB2

10: INA2 only

01: INB2 only

00: 800 ohm termination

3--- Reserved

2:0 GAIN2[2:0] Amplifier 2 Gain

111: reserved

110: 64x

101: 32x

100: 16x

011: 8x

010: 4x

001: 2x

000: 1x

Address: 0x02

-- Not defined

(read as 0)

R Readable

WWritable

R/W Readable

and Writable

Bits in bottom rows

are reset condition

Reset Condition : 0000_0000 (0x00) : Default value

Normal Operation : 00MM_0GGG : MUX and GAIN select

Power Down Operation : 1000_0000 (0x80) : PWDN enabled