Instruction Manual

CS5374
CS5374
11
DIGITAL CHARACTERISTICS (CONT.)
Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically
enters a power-down state. See Power Supply Characteristics for typical power-down timing.
24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,
synchronization instant (t
0
) is on the next MCLK rising edge.
25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.
Parameter Symbol Min Typ Max Unit
Master Clock Input
MCLK Frequency (Note 23)f
MCLK
- 2.048 - MHz
MCLK Duty Cycle MCLK
DTC
40 - 60 %
MCLK Rise Time t
RISE
- - 50 ns
MCLK Fall Time t
FALL
- - 50 ns
MCLK Jitter (in-band or aliased in-band) MCLK
IBJ
--300ps
MCLK Jitter (out-of-band) MCLK
OBJ
--1 ns
Master Sync Input
MSYNC Setup Time to MCLK Falling (Note 24)t
MSS
20 366 - ns
MSYNC Period (Note 24)t
MSYNC
40 976 - ns
MSYNC Hold Time after MCLK Falling (Note 24)t
MSH
20 610 - ns
MDATA Output
MDATA Output Bit Rate f
MDATA
-512-kbits/s
MDATA Output One’s Density Range (Note 22)MDAT
1D
14 - 86 %
Full-scale Output Code, Offset Corrected (Note 25)MDAT
FS
0xA2E736 - 0x5D18CA
MCLK
MSYNC
t
0
t
MSS
1 / f
MCLK
t
MSYNC
t
MSH
MDATA
MFLAG
1 / f
MDATA
Figure 7. MCLK / MSYNC Timing Detail