Instruction Manual

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Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

Dual High-performance Amplifier &

ΔΣ

Modulator

Features

 High Input Impedance Differential Amplifier

• Ultra-low input bias: < 1 pA

• Max signal amplitude: 5 Vpp differential

 Fourth Order Delta-Sigma (ΔΣ) Modulator

• Signal Bandwidth: DC to 2 kHz

• Common mode rejection: 110 dB CMRR

 Differential Analog Input, Digital ΔΣ Output

• Multiplexed inputs: INA, INB, 800Ω termination

• Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x

 Excellent Amplifier Noise Performance

•1.5 μVpp between 0.1 Hz and 10 Hz

• 11 nV /

√Hz from 200 Hz to 2 kHz

 High Modulator Dynamic Range

• 126 dB SNR @ 215 Hz BW (2 ms sampling)

• 123 dB SNR @ 430 Hz BW (1 ms sampling)

 Low Total Harmonic Distortion

• –118 dB THD typical (0.000126%)

• –108 dB THD maximum (0.0004%)

 Low Power Consumption

• Normal operation: 6.5 mA per channel

• Power down: 15 μA per channel max

 Dual Power Supply Configuration

• VA+ = +2.5 V; VA– = –2.5 V; VD = +3.3 V

Description

The CS5374 combines two marine seismic analog mea-

surement channels into one 7 mm x 7 mm QFN

package. Each measurement channel consists of a high

input impedance programmable gain differential amplifi-

er that buffers analog signals into a high-performance,

fourth-order ΔΣ modulator. The low-noise ΔΣ modulator

converts the analog signal into a one-bit serial bit stream

suitable for the CS5376A digital filter.

Each amplifier has two sets of external inputs, INA and

INB, to simplify system design as inputs from a hydro-

phone sensor or the CS4373A test DAC. An internal

800Ω termination can also be selected for noise tests.

Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x,

32x, 64x) and match the CS4373A test DAC output at-

tenuation settings for full-scale testing at all gain ranges.

Both the input multiplexer and gain are set by registers

accessed through a standard SPI™ port.

Each fourth-order ΔΣ modulator has very high dynamic

range combined with low total harmonic distortion and

low power consumption. It converts differential analog

signals from the amplifier to an oversampled ΔΣ serial bit

stream which is decimated by the CS5376A digital filter

to a 24-bit output at the final output word rate.

ORDERING INFORMATION

See page 43.

INA1+

INB1+

MUX1

MUX2

INB1-

INA1-

GUARD1

400 Ω 400 Ω

INA2+

INB2+

INB2-

INA2-

400 Ω 400 Ω

Reset, Clock,

and

Synchronization

INR1- VA+

MFLAG1

MCLK

MSYNC

MFLAG2

MDATA2

GAIN1GAIN2

GUARD2 INR2- INR2+

Order

Modulator

Order

Modulator

INF1- INF1+INR1+

RST

SPI

Serial

Interface

SDI

SDO

SCLK

INF2+INF2-OUT2-OUT2+

OUT1+ OUT1-

CS5374

VA-

GND

VREF-VREF+

VA+

VA-

MDATA1

SEP '10

DS862F2

CS5374

Summary of content (44 pages)

PAGE 1
CS5374 Dual High-performance Amplifier & ΔΣ Modulator Features Description  High Input Impedance Differential Amplifier The CS5374 combines two marine seismic analog measurement channels into one 7 mm x 7 mm QFN package. Each measurement channel consists of a high input impedance programmable gain differential amplifier that buffers analog signals into a high-performance, fourth-order ΔΣ modulator.
PAGE 2
CS5374 CS5374 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4 SPECIFIED OPERATING CONDITIONS ................................................................................ 4 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 4 THERMAL CHARACTERISTICS .............................................................................................
PAGE 3
CS5374 CS5374 8.4 PCB Layers and Routing............................................................................................... 33 8.5 Power Supply Rejection ................................................................................................ 33 8.6 SCR Latch-up Considerations....................................................................................... 33 8.7 DC-DC Converters .......................................................................................................
PAGE 4
CS5374 CS5374 1. CHARACTERISTICS AND SPECIFICATIONS • Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. • Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. • GND = 0 V, all voltages with respect to 0 V. • Device connected as shown in Figure 11 and Figure 12 unless otherwise noted.
PAGE 5
CS5374 CS5374 THERMAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit TA -10 - 70 °C Storage Temperature Range TSTR -65 - 150 °C Allowable Junction Temperature TJCT - - 125 °C θJA - 26 - °C / W Symbol Min Typ Max Unit BW DC - 2000 Hz GAIN x1 - x64 GAINCM - x1 - Vcm - (VA-)+2.5 - V VIN (VA-)+0.7 (VA-)+0.7 - (VA+)-1.25 (VA+)-1.75 V VINFS - - 5 2.5 1.25 625 312.5 156.25 78.
PAGE 6
CS5374 CS5374 ANALOG CHARACTERISTICS (CONT.) Parameter Symbol Min Typ Max Unit VBW DC - 2000 Hz Modulator Inputs Input Signal Frequencies (Note 9) Full-scale Differential AC Input VAC - - 5 Vpp Full-scale Differential DC Input VDC -2.5 - 2.5 VDC Input Common Mode Voltage VCM - (VA-)+2.5 - V Input Voltage Range (Vcm ± Signal ) VRNG (VA-)+0.7 - (VA+)-1.
PAGE 7
CS5374 CS5374 PERFORMANCE SPECIFICATIONS Parameter Symbol Min Typ Max Unit Amplifier Noise Voltage Noise f0 = 0.1 Hz to 10 Hz VNPP - 1.
PAGE 8
CS5374 CS5374 PERFORMANCE SPECIFICATIONS (CONT.) CS5374 Parameter Symbol Min Typ Max Unit Channel Gain Accuracy Channel Gain, Offset Corrected (Note 3, 14) GAINLSB -6101194 0xA2E736 - 6101194 0x5D18CA LSB LSB Absolute Gain Accuracy (Note 3, 15) GAINABS - ±1 +2 % Relative Gain Accuracy (Note 16) 2x 4x 8x 16x 32x 64x GAINREL -0.3 - -0.1 -0.1 0.1 0.4 0.4 0.3 0.
PAGE 9
CS5374 CS5374 CHANNEL PERFORMANCE PLOTS Figure 3. CS5374 Noise Performance (1x Gain) Figure 4.
PAGE 10
CS5374 CS5374 DIGITAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit - VD V Digital Inputs High-level Input Voltage (Note 21) VIH 0.6*VD Low-level Input Voltage (Note 21) VIL 0.0 - 0.8 V Input Leakage Current IIN - ±1 ±10 μA Digital Input Capacitance CIN - 9 - pF Input Rise Times Except MCLK tRISE - - 100 ns Input Fall Times Except MCLK tFALL - - 100 ns High-level Output Voltage, Iout = -40 μA VOH VD - 0.
PAGE 11
CS5374 CS5374 DIGITAL CHARACTERISTICS (CONT.) Parameter Symbol Min Typ Max Unit fMCLK - 2.
PAGE 12
CS5374 CS5374 SPI™ INTERFACE TIMING (EXTERNAL MASTER) Parameter Symbol Min Typ Max Unit CS Enable to Valid Latch Clock t1 60 - - ns Data Set-up Time Prior to SCK Rising t2 60 - - ns Data Hold Time After SCK Rising t3 60 - - ns SCK High Time t4 120 - - ns SCK Low Time t5 120 - - ns SCK Falling Prior to CS Disable t6 60 - - ns SCK Falling to New Data Bit t7 - - 90 ns SCK High Time t8 120 - - ns SCK Low Time t9 120 - - ns SCK Falling Hold Time Prior t
PAGE 13
CS5374 CS5374 POWER SUPPLY CHARACTERISTICS Parameter Symbol Min Typ Max Unit Power Supply Current, ch1 + ch2 combined Analog Power Supply Current (Note 26) IA - 13 16 mA Digital Power Supply Current (Note 26) ID - 50 100 μA Analog Power Supply Current (Note 26) IA - 6.
PAGE 14
CS5374 CS5374 CS5374 Hydrophone Sensor Hydrophone Sensor M U X AMP M U X AMP DS Modulator DS Modulator CS5376A Microcontroller or Configuration EEPROM Digital Filter CS5374 Hydrophone Sensor Hydrophone Sensor M U X AMP M U X AMP System Telemetry DS Modulator CS4373A DS Modulator Test DAC Figure 10. CS5374 System Block Diagram 2. GENERAL DESCRIPTION The CS5374 combines two marine seismic analog measurement channels into one 7 mm x 7 mm QFN package.
PAGE 15
CS5374 CS5374 680 Ω VA- 680 Ω 0.02 μF C0G 680 Ω 0.02 μF C0G VA+ 0.1μF 680 Ω GUARD1 0.1 μF 400 Ω 4th Order ΔΣ Modulator + INB2+ 4th Order ΔΣ Modulator - Hydrophone Sensor 400 Ω MUX2 INA2+ INA2- MSYNC OUT2+ MFLAG1 0.01μF To CS5376A Digital Control MDATA2 MFLAG2 SDO SPITM Serial Communications Interface + MDATA1 GND + 400 Ω INB2- A MCLK VD+ CS5374 VA+ VA- VA0.
PAGE 16
CS5374 CS5374 OUT1+ OUT1- GUARD1 GAIN1 + - 400 Ω INA1+ INB1+ 400 Ω MUX1 INA1INB1- + Figure 13. CS5374 Amplifier Block Diagram 3. AMPLIFIER OPERATION The CS5374 high-impedance, low-noise CMOS differential input, differential output amplifiers are optimized for precision analog signals between DC and 2 kHz. They have multiplexed inputs and programmable gains of 1x, 2x, 4x, 8x, 16x, 32x, and 64x.
PAGE 17
CS5374 CS5374 selected differential input signal, and will vary as the signal common mode varies. The GUARD output will not drive a significant load, as it can only provide a shielding voltage. 3.3 Differential Signals Analog signals into and out of the amplifiers are differential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full-scale 5 Vpp differential signal centered on a –0.15 V common mode can have: SIG+ = –0.15 V + 1.25 V = 1.1 V SIG– = –0.
PAGE 18
CS5374 CS5374 INR1- INF1- INF1+INR1+ VREF+ VREF- Reset, Clock, and Synchronization 4th Order Modulator RST MCLK MSYNC MDATA1 MFLAG1 Figure 14. CS5374 Modulator Block Diagram 4. MODULATOR OPERATION The CS5374 modulators are fourth-order ΔΣ type optimized for extremely high-resolution measurement of signals between DC and 2000 Hz.
PAGE 19
CS5374 CS5374 4.2 Modulator Inputs — INR, INF The modulator analog inputs are separated into differential rough and fine signals (INR±, INF±) to maximize sampling accuracy. The positive half of the differential input signal is connected to INR+ and INF+, while the negative half is attached to INF– and INR–. The INR± pins are switched-capacitor ‘rough charge’ inputs that pre-charge the internal analog sampling capacitor before it is connected to the INF± fine input pins. 4.2.
PAGE 20
CS5374 CS5374 offset and the modulator internal offset are removed from the final conversion result. Modulator Differential Analog Input Signal > + (VREF+5%) CS5376A Digital Filter 24-Bit Output Code Offset Corrected CH1 –60 mV Offset CH2 –35 mV Offset Error Flag Possible + VREF 5D18CA 5ADCCE 5BCB22 0V 000000 FDC404 FEB258 – VREF A2E736 A0AB3A A1998E > – (VREF+5%) Error Flag Possible Table 1. 24-bit Output Coding for the CS5374 Modulator and CS5376A Digital Filter Combination 4.
PAGE 21
CS5374 CS5374 RST Hardware Configuration SPI Registers Serial Pin Logic CS SCLK SDI SDO Figure 15. SPI Interface Block Diagram 5. SPITM SERIAL PORT The CS5374 SPI interface is a slave serial port designed to interface with the CS5376A SPI 2 port. SPI commands from the CS5376A write and read the CS5374 configuration registers to control hardware operation. 5.
PAGE 22
CS5374 CS5374 Instruction Opcode Address Definition Write 0x02 ADDR[7:0] Write SPI register specified by the address in ADDR. Read 0x03 ADDR[7:0] Read SPI register specified by the address in ADDR.
PAGE 23
CS5374 CS5374 Name Addr. Type # Bits Description VERSION 0x00 R 8 Device Version ID AMP1CFG 0x01 R/W 8 Amplifier 1 configuration AMP2CFG 0x02 R/W 8 Amplifier 2 configuration ADCCFG 0x03 R/W 8 Modulator 1 & 2 configuration PWRCFG 0x04 R/W 8 Power configuration Table 2. SPI Configuration Registers 5.3 SPI Registers 5.3.2 The CS5374 SPI registers are 8-bit registers that control the CS5374 hardware configuration.
PAGE 24
CS5374 CS5374 5.3.4 5.3.5 ADCCFG — 0x03 PWRCFG — 0x04 The ADCCFG register can disable modulator OFST and enable HP mode. It also enables PWDN mode for the channel 1 & 2 modulators. The PWRCFG register can vary bias currents for the amplifier and modulator to minimize power consumption.  Reset Condition : 0000_0000  Reset Condition : 0000_0000  Normal Operation : 0100_0000  Normal Operation : 1000_1111  Power Down Operation : 0011_0000  Power Down Operation : 0000_0000 5.
PAGE 25
CS5374 CS5374 5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port The CS5374 SPI port was designed to connect to the CS5376A secondary SPI 2 port as shown in Figure 12 on page 15. contain internal commands to write the CS5376A digital filter registers that control the SPI 2 hardware and enable the chip selects. The CS5376A SPI 2 hardware is controlled by writing internal digital filter registers SPI2CTRL, SPI2CMD, and SPI2DAT through a primary SPI 1 port.
PAGE 26
CS5374 CS5374 The SPI2DAT register is 24-bits wide and can contain up to three bytes of data to follow the SPI opcode and address. For configuring the CS5374, however, only one data byte per register address is required and is written aligned with the upper byte (i.e. 0x8F0000). The SPI2CTRL register is 24-bits wide and configures/controls the SPI 2 hardware, with bit assignments detailed in the CS5376A data sheet.
PAGE 27
CS5374 CS5374 Transaction CS5376A Primary SPI 1 Write 01 MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 02 MISO: ----------------------------------------------------------- 02 Delay 1ms, monitor SINT, or poll E2DREQ 03 MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 20 00 00 MISO: ----------------------------------------------------------- 04 Delay 1ms, monitor SINT, or poll E2DREQ 05 MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 Delay 1m
PAGE 28
CS5374 CS5374 Transaction CS5376A Primary SPI 1 Write 01 MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 04 MISO: ----------------------------------------------------------- 02 Delay 1ms, monitor SINT, or poll E2DREQ 03 MOSI: 02 | 03 | 00 00 01 | 00 00 12 | 8F 00 00 MISO: ----------------------------------------------------------- 04 Delay 1ms, monitor SINT, or poll E2DREQ 05 MOSI: 02 | 03 | 00 00 01 | 00 00 10 | 3F 01 61 MISO: ----------------------------------------------------------- 06 Delay 1m
PAGE 29
CS5374 CS5374 POWER DOWN MODE MCLK = OFF PWDN registers = X NORMAL OPERATION POWER DOWN MODE MCLK = ON PWDN registers = disabled MCLK = ON PWDN registers = enabled Figure 17. Power Mode Diagram 6. POWER MODES The CS5374 amplifiers and modulators have three power modes. Normal operation, power down with MCLK enabled, and power down with MCLK disabled. Power down mode is controlled by PWDN bits in the SPI registers, and are active high.
PAGE 30
CS5374 CS5374 From VA+ Regulator 100 μF 0.1 μF 10 Ω 2.500 V VREF From VARegulator 100 μF 0.1 μF Route VREF± as a differential pair from the 100uF RC filter capacitor + 100 μF 0.1 μF 0.1 μF 0.1 μF To VREF+ To VREF- Figure 18. Voltage Reference Circuit 7. VOLTAGE REFERENCE The CS5374 modulators require a 2.500 V precision voltage reference to be supplied to the VREF± pins. 7.
PAGE 31
CS5374 CS5374 1 / [(2.048 MHz) x (15 pF)] = 32 kΩ. While the size of the internal capacitor is fixed, the voltage reference input impedance can vary with MCLK. The voltage reference external RC filter series resistor creates a voltage divider with the VREF input impedance to reduce the effective applied input voltage. To minimize gain error resulting from this voltage divider effect, the RC filter series resistor should be the minimum size recommended in the voltage reference device data sheet. 7.
PAGE 32
CS5374 CS5374 0.1 uF To VA+ Regulator To VD Regulator 100 uF 0.1 uF 0.01 uF VA+ VA+ 100 uF VD+ CS5374 VA- VA- GND To VARegulator 0.1 uF 100 uF 0.1 uF Figure 19. Power Supply Diagram 8. POWER SUPPLIES The CS5374 has two positive analog power supply pins (VA+), two negative analog power supply pins (VA–), a digital power supply pin (VD+), and a ground pin (GND). For proper operation, power must be supplied to all power supply pins, and the ground pin must be connected to system ground.
PAGE 33
CS5374 CS5374 regulator output, with additional power supply bulk capacitance placed among the analog component route if space permits. 8.4 PCB Layers and Routing The CS5374 is a high-performance device, and special care must be taken to ensure power and ground routing is correct. Power can be supplied either through dedicated power planes or routed traces.
PAGE 34
CS5374 CS5374 9. SPITM REGISTER SUMMARY The CS5374 Configuration Registers contain the hardware configuration settings. Name 34 Addr.
PAGE 35
CS5374 CS5374 9.1 VERSION: 0x00 Figure 20.
PAGE 36
CS5374 CS5374 9.2 AMP1CFG: 0x01 Figure 21.
PAGE 37
CS5374 CS5374 9.3 AMP2CFG: 0x02 Figure 22.
PAGE 38
CS5374 CS5374 9.4 ADCCFG: 0x03 Figure 23.
PAGE 39
CS5374 CS5374 Figure 24.
PAGE 40
CS5374 CS5374 37 38 39 40 41 42 43 44 45 1 36 2 35 3 34 4 33 THERMAL PAD 5 6 7 32 31 30 CONNECT TO VA- 8 9 29 28 24 23 22 21 20 MCLK MSYNC MDATA1 MFLAG1 VD+ GND MDATA2 MFLAG2 SDO SDI SCLK CS GUARD2 OUT2+ OUT2INR2INF2INF2+ INR2+ NC VREF+ VREFNC NC 19 25 18 12 17 26 16 11 15 27 14 10 13 INA1+ INA1INB1INB1+ DNC VA+ VADNC INB2+ INB2INA2INA2+ 46 48 Pin 1 Location Indicators 47 GUARD1 OUT1+ OUT1INR1INF1INF1+ INR1+ NC VAVA+ NC RST 10.
PAGE 41
CS5374 CS5374 Differential Amplifier Analog Outputs OUT1–, OUT1+ 46 47 O Channel 1 differential analog output. GUARD1 48 O Guard output voltage for analog input Channel 1. GUARD2 13 O Guard output voltage for analog input Channel 2. OUT2+, OUT2– 14 15 O Channel 2 differential analog output. Modulator Analog Inputs INR1+, INF1+, INF1–, INR1– 42 43 44 45 I Channel 1 analog differential rough and fine inputs. From the Channel 1 differential anti-alias filter.
PAGE 42
CS5374 CS5374 11.
PAGE 43
CS5374 CS5374 12. ORDERING INFORMATION Model Number Temperature Package CS5374-CNZ, lead (Pb) free -10 to +70 °C 48-Pin QFN 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5374-CNZ, lead (Pb) free 260 °C 3 7 Days * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
PAGE 44
CS5374 CS5374 14. REVISION HISTORY Revision Date Changes T1 AUG 2008 Initial release of Target data sheet. A1 DEC 2008 Initial release of Advanced data sheet. A2 JAN 2009 Update to include more complete characterization data. PP1 APR 2009 Specify operation for 2.048 MHz MCLK and HP mode. Add PWRCFG register. Update to include more complete characterization data. F1 OCT 2009 Update to include final characterization data.