User Manual

CS5371A CS5372A
10 DS748F3
DIGITAL CHARACTERISTICS (CONT.)
Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power-
down state.
21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant
(t
0
) is on the next MCLK rising edge.
22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter.
Parameter Symbol Min Typ Max Unit
Master Clock Input
MCLK Frequency (Note 20)f
CLK
-2.048- MHz
MCLK Period (Note 20)t
mclk
-488- ns
MCLK Duty Cycle (Note 9)MCLK
DC
40 - 60 %
MCLK Rise Time (Note 9)t
RISE
--50ns
MCLK Fall Time (Note 9)t
FALL
--50ns
MCLK Jitter (in-band or aliased in-band) (Note 9)MCLK
IBJ
--300ps
MCLK Jitter (out-of-band) (Note 9)MCLK
OBJ
--1 ns
Master Sync Input
MSYNC Setup Time to MCLK Falling (Note 9, 21)t
mss
20 122 - ns
MSYNC Period (Note 9, 21)t
msync
40 976 - ns
MSYNC Hold Time after MCLK Falling (Note 9, 21)t
msh
20 122 - ns
MDATA Output
MDATA Output Bit Rate f
mdata
- 512 - kbits/s
MDATA Output Bit Period t
mdata
- 1953 - ns
MDATA Output One’s Density Range (Note 9)MDAT
OD
14 - 86 %
Full-scale Output Code (Note 22)MDAT
FS
0xA2EBE0
-
0x5D1420