Owner's manual

16 DS624F5
CS5368
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; C
L
= 20 pF, timing threshold is 50% of VLS.
Notes:
1. TDM Quad-Speed Mode only specified to operate correctly at VLS  3.14 V.
2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
Clocking” on page 10.
3. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaran-
teed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25.
Figure 4. TDM Timing
Parameter Symbol Min Typ Max Unit
Sample Rates Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
1
-
-
-
2
54
108
-
-
-
54
108
216
kHz
kHz
kHz
Master Mode
SCLK Frequency
SCLK Period 1/(256*216 kHz)
SCLK Duty Cycle (Note 2) (CLKMODE = 0)(Note 3)
(CLKMODE = 1)(Note 3)
t
PERIOD
t
HIGH1
t
HIGH1
256*Fs
18
40
28
-
-
50
33
256*Fs
-
60
38
Hz
ns
%
%
FS setup before SCLK rising (Single-Speed Mode)
FS setup before SCLK rising (Double-Speed Mode)
FS setup before SCLK rising (Quad-Speed Mode)
FS width in SCLK cycles
t
SETUP1
t
SETUP1
t
SETUP1
t
HIGH2
20
18
5
128
-
-
-
-
-
-
-
128
ns
ns
ns
-
SDOUT setup before SCLK rising
SDOUT hold after SCLK rising
t
SETUP2
t
HOLD2
5
5
-
-
-
-
ns
ns
Slave Mode
SCLK Frequency (Note 4)
SCLK Period 1/(256*216 kHz)
SCLK Duty Cycle
t
PERIOD
t
HIGH1
-
18
28
256*Fs
-
-
-
-
65
Hz
ns
%
FS setup before SCLK rising (Single-Speed Mode)
FS setup before SCLK rising (Double-Speed Mode)
FS setup before SCLK rising (Quad-Speed Mode)
FS width in SCLK cycles
t
SETUP1
t
SETUP1
t
SETUP1
t
HIGH2
20
20
10
1
-
-
-
-
-
-
-
244
ns
ns
ns
-
SDOUT setup before SCLK rising
SDOUT hold after SCLK rising
t
SETUP2
t
HOLD2
5
5
-
-
-
-
ns
ns
FS
SDOUT
SCLK
data data
t
HOLD2
t
SETUP2
t
SETUP1
new frame
data
t
PERIOD
t
HIGH1
t
HIGH2