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Preliminary Product Information

This document contains information for a product under development.

Cirrus Logic reserves the right to modify this product without notice.

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103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux

ADC Features

 Multi-bit Delta–Sigma Modulator

 103 dB Dynamic Range

 -95 dB THD+N

 Stereo 6:1 Input Multiplexer

 Programmable Gain Amplifier (PGA)

– ± 12 dB Gain, 0.5-dB Step Size

– Zero-crossing, Click-free Transitions

 Stereo Microphone Inputs

– +32 dB Gain Stage

– Low-noise Bias Supply

 Up to 192 kHz Sampling Rates

 Selectable 24-bit, Left-justified or I²S Serial

Audio Interface Formats

System Features

 Power-down Mode

 +5 V Analog Power Supply, Nominal

 +3.3 V Digital Power Supply, Nominal

 Direct Interface with 3.3 V to 5 V Logic Levels

 Pin Compatible with CS5345 (*See Section 2

for details.)

General Description

The CS5346 integrates an analog multiplexer, program-

mable gain amplifier, and stereo audio analog-to-digital

converter. The CS5346 performs stereo analog-to-digi-

tal (A/D) conve rsion of 24-bit serial values at sa mple

rates up to 192 kHz.

A 6:1 stereo input multiplexer is included for selecting

between line-level and microphone-level inputs. The

microphone input path includes a +32 dB gain stage

and a low-noise bias voltage supply. The PGA is avail-

able for line or microphone inputs and provides

gain/attenuation of ±12 dB in 0.5 dB steps.

The output of the PGA is followed by an advanced 5th-

order, multi-bit delta-sigma modulator and digital filter-

ing/decimation. Sampled data is transmitted by the

serial audio interface at rates from 8 kHz to 192 kHz in

either Slave or Master Mode.

Integrated level translators allow easy interfacing be-

tween the CS5346 and other devices operating over a

wide range of logic levels.

The CS5346 is available in a 48-pin LQFP package in

Commercial (-40° to +85° C) grade. The CDB5346 Cus-

tomer Demonstration board is also available for device

evaluation and implementation suggestions. Please re-

fer to “Ordering Information” on page 38 for complete

details.

3.3 V to 5 V

Low-Latency

Anti-Alias Filter

Internal Voltage

Reference

Multibit

Oversampling

ADC

Multibit

Oversampling

ADC

Low-Latency

Anti-Alias Filter

High Pass

Filter

High Pass

Filter

Stereo Input 1

Serial

Audio

Output

3.3 V 5 V

MUX

PCM Serial Interface

Level

Translator

Stereo Input 2

Stereo Input 3

Stereo Input 4 /

Mic Input 1 & 2

Stereo Input 5

Stereo Input 6

PGA

+32 dB

Level Translator

Reset

I²C/SPI

Control Data

Interrupt

Overflow

Left PGA Output

Right PGA Output

PGAA

AUG ‘12

DS861PP3

CS5346

Summary of content (38 pages)

PAGE 1
CS5346 103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux ADC Features General Description  Multi-bit Delta–Sigma Modulator The CS5346 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital converter. The CS5346 performs stereo analog-to-digital (A/D) conve rsion of 24-bit serial values at sa mple rates up to 192 kHz.  103 dB Dynamic Range  -95 dB THD+N  Stereo 6:1 Input Multiplexer  Programmable Gain Amplifier (PGA) – ± 12 dB Gain, 0.
PAGE 2
CS5346 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................
PAGE 3
CS5346 7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 30 7.7 Channel A PGA Control - Address 08h .......................................................................................... 31 7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 31 7.8 ADC Input Control - Address 09h .....................................................................
PAGE 4
CS5346 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 19 Table 2. Common Clock Frequencies ....................................................................................................... 19 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 20 Table 4. Device Revision ................................
PAGE 5
CS5346 NC NC NC NC SDOUT SCLK LRCK MCLK DGND VD INT OVFL 1.
PAGE 6
CS5346 AIN1A AIN1B 11 12 Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specification table. AGND 13 Analog Ground (Input) - Ground reference for the internal analog section. VA 14 Analog Power (Input) - Positive power for the internal analog section. AFILTA 15 Anti-alias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
PAGE 7
CS5346 2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES TSTI NC NC NC SDOUT SCLK LRCK MCLK DGND VD INT OVFL The CS5346 is p in compatible with the CS5345 and is a drop in replacement for CS5345 applications where VA = 5 V, VD = 3.3 V, VLS  3.3 V, and VLC  3.3 V. The pinout diagram and table below show the requirements for the remaining pins when replacing the CS5345 in these designs with a CS5346.
PAGE 8
CS5346 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters Symbol Min Nom Max Units Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) Commercial VA VD VLS VLC TA 4.75 3.13 3.13 3.13 -40 5.0 3.3 3.3 3.3 - 5.25 3.47 5.25 5.25 +85 V V V V C DC Power Supplies: ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V All voltages with respect to ground.
PAGE 9
CS5346 ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V; TA = +25° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz; PGA gain = 0 dB; All connections as shown in Figure 7 on page 18.
PAGE 10
CS5346 ANALOG CHARACTERISTICS CONT. Parameter Line-Level Input and Programmable Gain Amplifier Symbol Min Typ Max Unit - 12 -4 - 0.5 - + 12 +4 0.4 0.85*VA dB V/V dB dB Vpp 28.8 - 36 5 43.2 38 - k k % A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 98 95 104 101 - dB dB - -80 -81 -41 -74 - dB dB dB A-weighted unweighted (Note 6) -1 dB THD+N -20 dB -60 dB 77 74 83 80 - dB dB -0.1dB 100 - -74 -60 -20 180 - -68 +0.
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CS5346 DIGITAL FILTER CHARACTERISTICS Parameter (Note 7) Symbol Min Typ Max Unit 0 - 0.4896 Fs - - 0.035 dB 0.5688 - - Fs 70 - - dB - 12/Fs - s 0 - 0.4896 Fs - - 0.025 dB Single-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd Double-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd 0.
PAGE 12
CS5346 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Symbol Min Typ Max Unit Power Supply Current (Normal Operation) VA = 5 V VD, VLS, VLC = 3.3 V IA ID - 41 23 50 28 mA mA Power Supply Current (Power-Down Mode) (Note 9) VA = 5 V VLS, VLC, VD = 3.3 V IA ID - 0.50 0.54 - mA mA Power Consumption (Normal Operation) VA = 5 V (Power-Down Mode) VD, VLS, VLC = 3.3 V VA = 5V; VD, VLS, VLC = 3.
PAGE 13
CS5346 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V. Parameters (Note 11) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 2 mA Low-Level Output Voltage at Io = 2 mA Input Leakage Current Input Capacitance Minimum OVFL Active Time Serial Port Control Port Serial Port Control Port Serial Port Control Port Serial Port Control Port Symbol Min Typ Max Units VIH VIH VIL VIL VOH VOH VOL VOL Iin 0.
PAGE 14
CS5346 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VLS, CL = 20 pF. (Note 12) Parameter Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Symbol Min Typ Max Unit Fs Fs Fs 8 50 100 - 50 100 200 kHz kHz kHz fmclk tclkhl 2.048 8 - 51.
PAGE 15
CS5346 LRCK Input t slr t sclkh t sclkl SCLK Input t sdo t sclkw SDOUT Figure 1. Master Mode Serial Audio Port Timing LRCK Output t slr SCLK Output t sdo SDOUT Figure 2. Slave Mode Serial Audio Port Timing Channel B - Right Channel A - Left LRCK SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3.
PAGE 16
CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs tsust 4.
PAGE 17
CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF. Parameter Symbol Min Max Units CCLK Clock Frequency fsck - 6.0 MHz RST Rising Edge to CS Falling tsrs 500 - ns CS High Time Between Transmissions tcsh 1.
PAGE 18
CS5346 4. TYPICAL CONNECTION DIAGRAM +3.3V 10 µF 0.1 µF 0.1 µF VD +3.3V to +5V 0.
PAGE 19
CS5346 5. APPLICATIONS 5.1 Recommended Power-Up Sequence 1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3. The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence. 5.
PAGE 20
CS5346 5.2.2 Master Mode As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8. MCLK Freq Bits MCLK ÷1 000 ÷1.5 001 ÷2 010 ÷3 011 ÷4 100 ÷256 00 ÷128 01 ÷64 10 LRCK FM Bits ÷4 00 ÷2 01 ÷1 10 SCLK Figure 8. Master Mode Clocking 5.2.3 Slave Mode In Slave Mode, SCLK and LRCK operate as inputs.
PAGE 21
CS5346 5.4 Analog Input Multiplexer, PGA, and Mic Gain The CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the PGA. Analog inputs 4A and 4B are able to insert a +32 dB (+40x) gain stage before the input multiplexer, allowing them to be used for microphone-level signals without the need for any external gain.
PAGE 22
CS5346 demonstrates a simple solution. The 1800 pF capacitors in the low-pass filter should be C0G or equivalent to avoid distortion issues CS5346 9 k  to 144 k  36 k  Analog Input + V CM A/ D Input Figure 10. CS5346 PGA CS5346 9 k  to 144 k  36 k  Analog Input 2. 2 µF 100 k V CM + A/ D Input Figure 11. 1 VRMS Input Circuit . 9 k to 144 k 36 k Analog Input 100  2.2 µF 100 k 1800 pF VCM + A/D Input Figure 12. 1 VRMS Input Circuit with RF Filtering 5.5.
PAGE 23
CS5346 5.6 PGA Auxiliary Analog Output The CS5346 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA, or alternatively, they may be set to high impedance. See the “PGAOut Source Select (Bit 6)” on page 30 for information on configuring the PGA auxiliary analog output. The PGA auxiliary analog output can source very little current.
PAGE 24
CS5346 dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high-impedance state). For both read and write cycles, the memory address pointer will automatically increment following each data byte in order to facilitate block reads and writes of successive registers.
PAGE 25
CS5346 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 1 0 0 1 STOP MAP BYTE 7 1 AD1 AD0 0 6 5 4 3 ACK 2 1 CHIP ADDRESS (READ) 1 0 0 0 1 ACK START DATA 1 AD1 AD0 1 START 7 ACK DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 16. Control Port Timing, I²C Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble.
PAGE 26
CS5346 5.9 Reset When RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the control port and registers, the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low-power state and begin operation.
PAGE 27
CS5346 6. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr 01h Function Chip ID pg. 28 02h Power Control pg.
PAGE 28
CS5346 7. REGISTER DESCRIPTION 7.1 Chip ID - Register 01h 7 PART3 6 PART2 5 PART1 4 PART0 3 REV3 2 REV2 1 REV1 0 REV0 Function: This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits (3 through 0) indicate the device revision as shown in Table 4 below. REV[3:0] Revision 0000 A1 Table 4. Device Revision 7.2 Power Control - Address 02h 7 Freeze 7.2.
PAGE 29
CS5346 7.3 ADC Control - Address 04h 7 6 5 4 3 2 1 0 FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S 7.3.1 Functional Mode (Bits 7:6) Function: Selects the required range of sample rates. FM1 FM0 0 0 Mode Single-Speed Mode: 8 to 50 kHz sample rates 0 1 Double-Speed Mode: 50 to 100 kHz sample rates 1 0 Quad-Speed Mode: 100 to 200 kHz sample rates 1 1 Reserved Table 6. Functional Mode Selection 7.3.
PAGE 30
CS5346 7.4 MCLK Frequency - Address 05h 7 Reserved 7.4.1 6 MCLK Freq2 5 MCLK Freq1 4 MCLK Freq0 3 2 1 0 Reserved Reserved Reserved Reserved Master Clock Dividers (Bits 6:4) Function: Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings. MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0 ÷1 0 0 0 ÷ 1.5 0 0 1 ÷2 0 1 0 ÷3 0 1 1 ÷4 1 0 0 Reserved 1 0 1 Reserved 1 1 x Table 8. MCLK Frequency 7.
PAGE 31
CS5346 7.7 Channel A PGA Control - Address 08h 7 Reserved 7.7.1 6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0 Channel A PGA Gain (Bits 5:0) Function: Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the ±12 dB range are reserved and must not be used. See Table 10 for example settings.
PAGE 32
CS5346 PGASoft 0 0 1 1 PGAZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default) Table 11. PGA Soft Cross or Zero Cross Mode Selection 7.8.2 Analog Input Selection (Bits 2:0) Function: These bits are used to select the input source for the PGA and ADC. Please see Table 12.
PAGE 33
CS5346 7.10.1 Clock Error (Bit 3) Function: Indicates the occurrence of a clock error condition. 7.10.2 Overflow (Bit 1) Function: Indicates the occurrence of an ADC overflow condition. 7.10.3 Underflow (Bit 0) Function: Indicates the occurrence of an ADC underflow condition. 7.
PAGE 34
CS5346 8. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
PAGE 35
CS5346 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 Amplitude (dB) Amplitude (dB) 9. FILTER PLOTS 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 Frequency (norm alized to Fs) 0 0.10 -1 0.08 -2 0.06 -3 0.04 -4 -5 -6 -7 0.58 0.60 0.00 -0.04 -0.06 -0.08 -0.10 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0 0.55 Figure 19.
PAGE 36
0 0.10 -1 0.08 -2 0.06 -3 0.04 Amplitude (dB) Amplitude (dB) CS5346 -4 -5 -6 -7 0.02 0.00 -0.02 -0.04 -8 -0.06 -9 -0.08 -10 0.46 0.47 0.48 0.49 0.50 0.51 -0.10 0.00 0.05 0.52 Frequency (norm alized to Fs) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Figure 24. Double-Speed Passband Ripple Amplitude (dB) Amplitude (dB) Figure 23. Double-Speed Transition Band (Detail) 0.0 0.
PAGE 37
CS5346 10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B  A A1 L DIM A A1 B D D1 E E1 e* L MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000°  * Nominal pin pitch is 0.50 mm INCHES NOM MAX MIN 0.055 0.063 --0.004 0.006 0.05 0.009 0.011 0.17 0.354 0.366 8.70 0.28 0.280 6.90 0.354 0.366 8.70 0.28 0.280 6.90 0.020 0.024 0.40 0.24 0.030 0.45 4° 7.000° 0.00° *Controlling dimension is mm. MILLIMETERS NOM MAX 1.40 1.60 0.10 0.15 0.22 0.27 9.0 BSC 9.30 7.0 BSC 7.10 9.0 BSC 9.
PAGE 38
CS5346 12.ORDERING INFORMATION Product CS5346 CDB5346 Description 24-bit, 192 kHz Stereo Audio ADC Package Pb-Free 48-LQFP CS5346 Evaluation Board Grade Temp Range Yes Commercial -40° to +85° C No - - Container Order # Tray CS5346-CQZ Tape & Reel CS5346-CQZR - CDB5346 13.REVISION HISTORY Release PP1 PP2 PP3 Changes -Updated Title -Added text to Section 2.