User Manual
24 DS658F4
CS5345
In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divid er MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM. Table 3
lists the appropr iat e dividers.
4.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
4.2.3 Slave Mode
In Slave Mode, SCLK and LRCK o perate as inputs. The Left/Righ t clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied ma ster clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 4 for required clock ra-
tios.
4.3 High-Pass Filter and DC Offs et Calibration
When using operational amplifiers in the input circuitry driving the CS5345, a small DC offset may be driven
into the A/D converte r. The CS5 345 includes a h igh-pa ss filter after the decimator to remove any DC offset
MCLK/LRCK Ratio MCLK Dividers
64x --÷1
96x --÷1.5
128x -÷1÷2
192x -÷1.5÷3
256x ÷1 ÷2 ÷4
384x ÷1.5 ÷3 -
512x ÷2 ÷4 -
768x ÷3 - -
1024x ÷4 - -
Mode SSM
DSM QSM
Table 3. MCLK Dividers
Single-Speed Double-Speed Quad-Speed
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x
Table 4. Slave Mode Serial Bit Clock Ratios
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK
FM Bits
MCLK Freq Bits
Figure 8. Master Mode Clocking