Manual

14 DS601F2
CS5340
Confidential Draft
3/11/08
3. TYPICAL CONNECTION DIAGRAM
FILT+
V
0.1
µ
F
A/D CONVERTER
SCLK
CS5340
MCLK
VQ
1
µ
F
+
RST
VA
L
1
µ
F
1.8 V to 5V
1
µ
F
+
+
SDOUT
GND
LRCK
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.1
µ
F
0.1
µ
F
0.1
µ
F
REFGND
1µ
F
+
AINL
AINR
3.3V to 5V
1
µ
F
+
0.1
µ
F
3.3V to 5V
Ω
5.1
V
D
0.1
µ
F
Ω
10k
VL or GND
* Pull-up to VL for I
2
S
Pull-down to GND for LJ
*
M0
M1
Analog Input Buffer
Figure 21
**
** Resistor may only be
used if VD is derived from
VA. If used, do not drive
any other logic from VD
***
*** Capacitor value affects
low frequency distortion
performance as described
in Section 4.8