User Manual

DS138F6 7
CS5330A/31A
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0V, Logic 1 = VA+; CL = 20 pF) Switching characteristics are guaranteed by characterization.
9.
10.
11.
Parameter Symbol Min Typ Max Unit
Output Sample Rate
Fs 2 - 50 kHz
MCLK Period MCLK/LRCK = 256
t
clkw 78 - 1000 ns
MCLK Low MCLK/LRCK = 256
t
clkl 31 - 1000 ns
MCLK High MCLK/LRCK = 256
t
clkh 31 - 1000 ns
MCLK Period MCLK/LRCK = 384
t
clkw 52 - 1000 ns
MCLK Low MCLK/LRCK = 384
t
clkl 20 - 1000 ns
MCLK High MCLK/LRCK = 384
t
clkh 20 - 1000 ns
MCLK Period MCLK/LRCK = 512
t
clkw 39 - 1000 ns
MCLK Low MCLK/LRCK = 512
t
clkl 13 - 1000 ns
MCLK High MCLK/LRCK = 512
t
clkh 13 - 1000 ns
MASTER MODE
SCLK falling to LRCK
t
mslr -10 - 10 ns
SCLK falling to SDATA valid
t
sdo -10 - 35 ns
SCLK Duty cycle
-50-%
SLAVE MODE
LRCK duty cycle
25 50 75 %
SCLK Period
t
clkw (Note 9) --ns
SCLK Pulse Width Low
t
clkl (Note 10) --ns
SCLK Pulse Width High
t
clkh 20 - - ns
SCLK falling to SDATA valid
t
dss - - (Note 11) ns
LRCK edge to MSB valid
t
lrdss - - (Note 11) ns
SCLK rising to LRCK edge delay
t
slr1 20 - - ns
LRCK edge to rising SCLK setup time
t
slr2 (Note 11) --ns
1
64 F
s
1
128 F
s
- 15 ns
1
256 F
s
+ 5 ns