Owner's manual

DS868PP2 Copyright 2008 Cirrus Logic, Inc. 17
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.12 Switching Characteristics — Serial Control Port - I
2
C Master Mode
Figure 6. Serial Control Port - I
2
C Master Mode Timing
Parameter Symbol Min Max Units
SCP_CLK frequency
1
1. The specification f
iicck
indicates the maximum speed of the hardware. The system designer should be aware that the
actual maximum speed of the communication port may be limited by the firmware application.
f
iicck
-400kHz
SCP_CLK low time t
iicckl
1.25 - µs
SCP_CLK high time t
iicckh
1.25 - µs
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
t
iicckcmd
1.25 µs
START condition to SCP_CLK falling t
iicstscl
1.25 - µs
SCP_CLK falling to STOP condition t
iicstp
2.5 - µs
Bus free time between STOP and START conditions t
iicbft
3-µs
Setup time SCP_SDA input valid to SCP_CLK rising t
iicsu
100 ns
Hold time SCP_SDA input after SCP_CLK falling t
iich
20 - ns
SCP_CLK low to SCP_SDA out valid t
iicdov
-18ns
S
CP_CLK
SCP_SDA
01 67801 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK
LSB
8
ACK
MSB
t
iicstp
6
t
iicdov
t
iicb
ft
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr