User guide

Booting the DSP in Master Boot Mode

CS4953x4/CS4970x4 System Designer’s Guide

Figure 1-4. Master Boot Flow

1.3.1.1 Master Boot Protocol

1. Set RESET Low. A download sequence is started when the host holds the RESET pin low for the

required time.

2. Wait for 1 uS.

3. Set RESET

High. As soon as Reset goes High, the SCP2 lines will start toggling and the DSP will

begin to boot from SPI Flash. The commands sent out to the SPI Flash are listed in Table 1-1

4. Wait for SCP1_IRQ to go Low.

5. Read the message from the DSP. Current DSP messages are described in Table 1-2.

6. If the Master boot is successful, the DSP will respond with the “Flash image verified” message

1. A “Flash image verified” message does not guarantee that the complete Flash image has been

programmed correctly or is bit-exact. This message only verifies that certain key words are at specified

locations. It is the user’s responsibility to ensure that the Flash is programmed correctly by reading the

contents of the Flash.

RESET (High)

Start

RESET (Low)

Wait 1 µS

Exit (Error)

Is SCP1_IRQ

Low?

Is Time

> 1 Sec?

READ_* (MSG)

Is Message =

Flash Image Verified?

DONE

Exit (Error)