User guide

DS810UM6 Copyright 2013 Cirrus Logic, Inc 1-3
Booting the DSP in Master Boot Mode
CS4953x4/CS4970x4 System Designer’s Guide
Table 1-2. Supported SPI Flash Read Format
Pin 11 (144-Pin
Package)
Cycle Type Operation
Max
Freq.
(MHz)
1
1. SCP2_SCLK is 12.288 MHz (based on 24.576 MHz in CLKIN) during initial boot and then switches to 50 MHz once the PLL is locked.
Bus Cycle
2
2. One bus cycle is eight clock periods.
12 3456 7 8 9
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
High
50 0x03 Hi-Z 0x00 Hi-Z 0x00 Hi-Z 0x00 Hi-Z
X
3
3. x = Don’t care
D
OUT
(Byte 0)
XD
OUT
(Byte 1)
XD
OUT
(Byte 2)
XD
OUT
(Byte 3)
XD
OUT
(Byte 4)
Low
50 0x68 Hi-Z 0x00 Hi-Z 0x00 Hi-Z 0x00 Hi-Z X Hi-Z X Hi-Z X Hi-Z X Hi-Z X D
OUT