CS4953x4/CS4970x4 32-bit Audio DSP Family CS4953x4/CS4970x4 System Designer’s Guide Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright 2013 Cirrus Logic, Inc. http://www.cirrus.
CS4953x4/CS4970x4 System Designer’s Guide Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable.
CS4953x4/CS4970x4 System Designer’s Guide Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-iii Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-vii Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS4953x4/CS4970x4 System Designer’s Guide Chapter 2. Serial Communication Mode.............................................................. 2-1 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.2 Communication Using the Serial Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.3 Serial Control Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CS4953x4/CS4970x4 System Designer’s Guide Chapter 5. External Memory Interfaces ............................................................... 5-1 5.1 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1.1 SDRAM Controller Interface ...........................................................................................5-2 5.1.2 SDRAM Interface Signals................................................................
CS4953x4/CS4970x4 System Designer’s Guide 8.3.2 Search paths Page .........................................................................................................8-5 8.3.3 Audio sources Page .......................................................................................................8-6 8.3.4 Sample rates Page .........................................................................................................8-7 8.3.5 Firmware components Page.........................................
CS4953x4/CS4970x4 System Designer’s Guide 9.2.2.4 Command Field .............................................................................................9-5 9.2.2.4.1 Hexadecimal Command ..................................................................9-5 9.2.2.4.2 Configuration File Commmand ........................................................9-5 9.2.2.4.3 Comments .......................................................................................9-5 9.2.2.5 Browse Button ....................
CS4953x4/CS4970x4 System Designer’s Guide C.1.5 Dolby Digital®PLus ....................................................................................................... C-3 C.1.5.1 Loading Dolby Digital Plus for Stereo Output............................................... C-3 C.1.5.2 Setting DRC Modes for Dolby Digial Plus .................................................... C-3 C.1.6 Dolby® TrueHD............................................................................................................
CS4953x4/CS4970x4 System Designer’s Guide Figure 2-7. Serial Control Port Internal Block Diagram ................................................................................2-9 Figure 2-8. Block Diagram of I2C System Bus ...........................................................................................2-10 Figure 2-9. I2C Start and Stop Conditions .................................................................................................2-11 Figure 2-10. I2C Address with ACK and NACK ...
CS4953x4/CS4970x4 System Designer’s Guide Figure 8-19. Displaying CDM Window .......................................................................................................8-25 Figure 8-20. DSP Response after Successful Master Boot .......................................................................8-27 Figure 8-21. Changing Concurrency Modes ..............................................................................................8-28 Figure 9-1. DSP Condenser Wizard Menu Items ............
CS4953x4/CS4970x4 System Designer’s Guide Table 3-2. Bursty Data Input (BDI) Pins .......................................................................................................3-3 Table 3-3. Input Data Format Configuration (Input Parameter A) ................................................................3-5 Table 3-4. Input SCLK Polarity Configuration (Input Parameter B) ..............................................................3-5 Table 3-5.
Introduction to CS4953x4/CS4970x4 System Designer’s Guide CS4953x4/CS4970x4 System Designer’s Guide Preface P.1 Introduction to CS4953x4/CS4970x4 System Designer’s Guide This design guide contains development guidelines for customers using the Cirrus Logic CS4953x4/ CS4970x4 DSP chip-set. All information needed to create a DSP application are presented in this consolidated documentation set.
Overview of the CS4953x4/CS4970x4 DSP CS4953x4/CS4970x4 System Designer’s Guide P.2.
Overview of the CS4953x4/CS4970x4 DSP CS4953x4/CS4970x4 System Designer’s Guide DSPB DSPA Arbiter SRAM / FLASH Controller CS4953x4 Debug Controller Stereo Audio Input/DSD Peripheral Bus Controller DAI Controller Stereo Audio Input/DSD Stereo Audio Input/DSD X Stereo Audio Input/DSD SRAM Ext (64 bit) ROM DAI2 DAI Controller SRAM Y ROM SRAM Memory Controller Arbiter Log/Exp SDRAM Controller Stereo Audio Input/DSD DAI1 Security X P Y ROM Stereo Audio Output DAO1 64 bit 32-bit Dual
CS4953x4/CS4970x4 Chip Functional Overview CS4953x4/CS4970x4 System Designer’s Guide P.3 CS4953x4/CS4970x4 Chip Functional Overview The CS4953x4/CS4970x4 chip support a maximum clock speed of 150 MHz in a 144-pin LQFP or 128pin LQFP package. A high-level functional description of the CS4953x4/CS4970x4 chip is provided in this section. P.3.
CS4953x4/CS4970x4 Chip Functional Overview CS4953x4/CS4970x4 System Designer’s Guide for compressed data input, custom internal hardware is enabled that off-loads some pre-processing of the incoming stream to help maximize the MIPS available in the DSP core for user-customized applications. P.3.7 Direct Stream Digital (DSD) Controller The DSD controller for the CS4953x4/CS4970x4 also has a DSD controller which allows the DSP to be integrated into a system that supports SACD audio.
Firmware Overview CS4953x4/CS4970x4 System Designer’s Guide P.3.11 DMA Controller The DMA controller contains 12 stereo channels. The O/S uses 11 stereo channels, 6 for the DAO (2 are for the S/PDIF transmitters), 4 for the DAI, and one for the parallel control port. The addition of the DMA channel for the parallel control port allows compressed audio data to be input over this port. The DMA block is able to move data to/from X or Y memory, or alternate between both X and Y memory.
CS40700x Pin Descriptions CS4953x4/CS4970x4 System Designer’s Guide P.4.2 DSP Condenser Cirrus Logic provides the customer with the DSP Condenser application to implement the design capabilities described in Section P.1. The DSP Condenser application is the vehicle that allows system designers to quickly program the CS4953x4/CS4970x4 DSP with the customer’s design and to access Cirrus Logic powerful firmware suite.
CS40700x Pin Descriptions CS4953x4/CS4970x4 System Designer’s Guide P.5.1.2 Ground For two-layer circuit boards, care should be taken to have sufficient grounding between the DSP and parts in which it will be interfacing (DACs, ADCs, S/PDIF Receivers, microcontrollers, and especially external memory). Insufficient grounding can degrade noise margins between devices resulting in data integrity problems. Table P-3.
CS40700x Pin Descriptions CS4953x4/CS4970x4 System Designer’s Guide P.5.2.2 PLL The internal phase locked loop (PLL) of the CS4953x4/CS4970x4 requires an external current reference resistor. The resistor is used to calibrate the PLL and must meet the tolerances specified below. The layout topology is shown in the typical connection diagrams.
CS40700x Pin Descriptions CS4953x4/CS4970x4 System Designer’s Guide Table P-7. DSP Core Clock Pins LQFP-144 Pin # LQFP-128 Pin # Pin Name Pin Type 123 16 XTAL_OUT Output 124 17 XTI Input Reference Clock Input/Crystal Oscillator Input. An external clock may be input directly to this pin or one end of a crystal may be connected to this pin. 125 18 XTO Output Crystal Oscillator Output. One end of a crystal oscillator is connected to this pin.
CS4970x4 Pin Assignments CS4953x4/CS4970x4 System Designer’s Guide Configuration and control of the CS4953x4/CS4970x4x decoder and its peripherals are indirectly executed through a messaging protocol supported by the operating system (OS) running on the DSP. In other words, successful communication can only be accomplished by following the low-level hardware communication format and high-level messaging protocol.
DS810UM6 Table P-10. CS4970x4 Pin Assignments for 144-Pin and 128-Pin Packages LQFP144 Pin # LQFP128 Pin # 1 - GPIO28 General Purpose Input/Output 2 - GPIO29 General Purpose Input/Output 3 36 DBDA Debug Data 4 37 DBCK Debug Clock Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type 3.3V (5V tol) BiDir 1. XMTA_IN 1. S/PDIF Pass-thru Input. Reset State IN 3.3V (5V tol) BiDir IN 3.3V (5V tol) In/OD IN 3.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 25 - Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions GPIO25 General Purpose Input/Output 1. UART_TXD 2. EE_CS 1. UART Output. 2. EEPROM Boot Chip Select. UART_RXD UART Input. Pwr Type Reset State 3.3V (5V tol) BiDir IN 3.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 60 89 VDDIO4 I/O power supply voltage 61 90 SD_A7 SDRAM Address Bit 7 EXT_A7 Flash Address Bit 7 EXT_A6 Flash Address Bit 6 Function 1 (Default) Description of Default Function 62 91 SD_A6 SDRAM Address Bit 6 63 92 GNDIO4 I/O ground 64 93 SD_A5 SDRAM Address Bit 5 Secondary Functions Description of Secondary Functions Pwr 3.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 93 121 94 122 Function 1 (Default) RESET GNDIO6 Description of Default Function Secondary Functions Description of Secondary Functions Chip Reset Pwr Type 3.3V (5V tol) In I/O ground 0V Copyright 2013 Cirrus Logic 95 123 GPIO33 General Purpose Input/Output SCP1_MOSI 96 - GPIO32 General Purpose Input/Output 1. SCP1_CS 2.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type Reset State 1. Parallel Control Port Address Bit 2 2. Parallel Control Port Address Bit 3.3V (5V tol) BiDir 10 3. SPI Mode Master Data Output/ Slave Data Input IN Copyright 2013 Cirrus Logic 106 - GPIO10 General Purpose Input/Output 1. PCP_A2 2.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 117 - GPIO3 General Purpose Input/Output - 10 GPIO3 General Purpose Input/Output 118 Function 1 (Default) Description of Default Function Secondary Functions 1. PCP_D3 2. PCP_AD3 1. Parallel Control Port Data Bus 2. Parallel Control Port Multiplexed Address and Data Bus - GPIO2 General Purpose Input/Output 1. PCP_D2 2. PCP_AD2 1.
DS810UM6 Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # Function 1 (Default) 138 30 DAI1_LRCLK PCM Audio Input Sample Rate (Left/ DSD4 Right) Clock 139 31 GNDIO8 I/O ground 140 - GPIO42 Description of Default Function Secondary Functions Copyright 2013 Cirrus Logic 1.PCM Audio Input Sample Rate Clock 2. Bursty Data Input Request 3. Parallel Control Port Interrupt 4. Parallel Port Bus 3.3V (5V tol) BiDir/OD IN 1.
DS810UM6 P.7 CS4953x4 Pin Assignments Table P-11 shows the names and functions for each pin. Table P-11. CS4953x4 Pin Assignments for 144-Pin and 128-Pin Packages LQFP144 Pin # LQFP128 Pin # 1 - GPIO28 General Purpose Input/ Output 2 - GPIO29 General Purpose Input/ Output 3 36 DBDA 4 37 Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type Reset State Pullup at Reset Copyright 2013 Cirrus Logic 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 17 49 GPIO15 General Purpose Input/ Output 18 50 VDDIO1 I/O power supply voltage 19 51 DAO1_DATA0 Digital Audio Output 0 20 52 DAO1_SCLK 21 53 Function 1 (Default) Description of Default Function Secondary Functions 1. DAO1_DATA1 2. HS1 Description of Secondary Functions Type Pullup at Reset IN Y Copyright 2013 Cirrus Logic 3.3V (5V tol) BiDir 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 38 66 EXT_WE Flash Write Enable 39 68 SD_D0 SDRAM Data Bit 0 EXT_D0 40 69 SD_D15 SDRAM Data Bit 15 41 70 SD_D14 42 71 43 Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type Reset State Pullup at Reset Copyright 2013 Cirrus Logic 3.3V (5V tol) OUT Flash Data Bit 0 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) Copyright 2013 Cirrus Logic LQFP144 Pin # LQFP128 Pin # 58 87 SD_A9 SDRAM Address Bit 9 EXT_A9 Flash Address Bit 9 3.3V (5V tol) OUT 59 88 SD_A8 SDRAM Address Bit 8 EXT_A8 Flash Address Bit 8 3.3V (5V tol) OUT 60 89 VDDIO4 I/O power supply voltage 3.3V PWR 61 90 SD_A7 SDRAM Address Bit 7 EXT_A7 Flash Address Bit 7 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) Copyright 2013 Cirrus Logic LQFP144 Pin # LQFP128 Pin # 79 108 SD_CAS SDRAM Column Address Strobe 3.3V (5V tol) OUT 80 109 SD_RAS SDRAM Row Address Strobe 3.3V (5V tol) OUT 81 110 SD_CS SDRAM Chip Select 3.3V (5V tol) OUT 82 111 EXT_A15 Flash Address Bit 15 3.3V (5V tol) OUT 83 112 VDD5 Core power supply voltage 1.8V PWR 84 113 EXT_A16 Flash Address Bit 16 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) Copyright 2013 Cirrus Logic Type Reset State Pullup at Reset 3.3V (5V tol) BiDir/OD IN Y 3.3V (5V tol) BiDir/OD IN Y 0V PWR 1. Serial Control Port 1 Input Busy 2. Parallel Control Port Input Busy 3.3V (5V tol) BiDir/OD IN Y 1. SCP1_BSY 1. Serial Control Port 1 Input Busy 3.3V (5V tol) BiDir/OD IN Y 1. PCP_WR 2. PCP_DS 3. SCP2_CLK 1. Parallel Port Write Select (Intel Mode) 2.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type Reset State Pullup at Reset 1. PCP_IRQ 2. SCP2_IRQ 1. Parallel Control Port Data Ready Interrupt Request 2. Serial Control Port Data Ready Interrupt Request 3.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # - 11 GPIO2 General Purpose Input/ Output 119 12 VDD7 Core power supply voltage 120 - GPIO1 General Purpose Input/ Output 1. PCP_D1 2.
DS810UM6 Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued) LQFP144 Pin # LQFP128 Pin # 138 30 DAI1_LRCLK PCM Audio Input Sample Rate (Left/Right) Clock 139 31 GNDIO8 I/O ground Function 1 (Default) Description of Default Function Secondary Functions DSD4 Description of Secondary Functions DSD Audio Input Data 4 Pwr Type 3.3V (5V tol) In 0V PWR Reset State Pullup at Reset Y 1.PCM Audio Input Sample Rate Clock 2. Bursty Data Input Request 3.
Overview CS4953x4/CS4970x4 System Designer’s Guide Chapter 1 Operational Modes 1.1 Overview The CS4953x4/CS4970x4 DSP has several operational modes that can be used to conform to many system configurations. The DSP is configured to Master Boot as shown in Figure 1-1 in order to simplify connectivity and to reduce the complexity of the microcontroller code used in the system.
Operational Mode Selection CS4953x4/CS4970x4 System Designer’s Guide http://www.datasheet4u.com/html/A/T/4/AT45DB041D_ATMELCorporation.pdf.html 1.2 Operational Mode Selection The operational mode for the CS4953x4/CS4970x4 is selected by the values of the HS[4:0] pins on the rising edge of RESET. This value determines the communication mode used until the part is reset again. This value also determines the method for loading application code.
DS810UM6 Table 1-2. Supported SPI Flash Read Format Bus Cycle2 Pin 11 (144-Pin Package) Cycle Type Operation High Low Max Freq.
DS810UM6 Copyright 2013 Cirrus Logic, Inc Booting the DSP in Master Boot Mode CS4953x4/CS4970x4 System Designer’s Guide 1-4 Figure 1-2.
DS810UM6 Copyright 2013 Cirrus Logic, Inc Booting the DSP in Master Boot Mode CS4953x4/CS4970x4 System Designer’s Guide 1-5 Figure 1-3.
Booting the DSP in Master Boot Mode CS4953x4/CS4970x4 System Designer’s Guide The typical connection diagram in Figure 1-2 and Figure 1-3 is shown with a microcontroller controlling the DSP in SPI mode. Details of the SPI protocol can be found in Section 2.4, "SPI Port" on page 2-1. An external SDRAM is also shown in Figure 1-2 and Figure 1-3 The external SDRAM is required for systems that require HD decoders. Care must be taken when routing this interface.
Booting the DSP in Master Boot Mode CS4953x4/CS4970x4 System Designer’s Guide Start RESET (Low) Wait 1 µS RESET (High) N Is SCP1_IRQ Low? N Is Time > 1 Sec? Y Exit (Error) Y READ_* (MSG) Is Message = Flash Image Verified? N Exit (Error) Y DONE Figure 1-4. Master Boot Flow 1.3.1.1 Master Boot Protocol 1. Set RESET Low. A download sequence is started when the host holds the RESET pin low for the required time. 2. Wait for 1 uS. 3. Set RESET High.
Booting the DSP in Master Boot Mode CS4953x4/CS4970x4 System Designer’s Guide 7. If the message is “Flash image verified,” then the DSP will be processing audio at this time from the default port. 1.3.1.2 Messages Read from CS4953x4/CS4970x4 Table 1-2 defines the boot read messages, in mnemonic and actual hex value, used in CS4953x4/ CS4970x4 boot sequences. Table 1-3.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Chapter 2 Serial Communication Mode 2.1 Introduction The CS4953x4/CS4970x4 uses the Serial Control Port (SCP) to communicate with external devices such as host microprocessors using either I2C or SPI serial communication formats. 2.2 Communication Using the Serial Control Port The SCP1 Port is configured as a Slave and the SCP2 Port is configured as a Master.
SPI Port CS4953x4/CS4970x4 System Designer’s Guide device on the bus may respond to one or more unique commands, and can operate as either a transmitter or receiver. A device is considered the Master in a transaction if it drives the CS pin of another device, and is also Mastering the SCP1_CLK line. A block diagram of the CS4953x4/CS4970x4 and CS4953x4/CS4970x4 SPI Serial Control Port is provided in Figure 2-1. Figure 2-1.
SPI Port CS4953x4/CS4970x4 System Designer’s Guide Table 2-1. Serial Control Port SPI Signals (Continued) Pin Name Pin Description LQFP-144 Pin # LQFP-128 Pin # Pin Type SCP2_CLK SPI Control Port Bit Clock In Master mode, this pin serves as the serial control clock output. In serial Slave mode, this pin serves as the serial control clock input. 103 1 I/O SCP2_MISO SPI Mode Master Data Input/Slave Data Output In SPI Slave mode this pin serves as the data input.
SPI Port CS4953x4/CS4970x4 System Designer’s Guide signal is low. The bus is free only when all Slave SCP1_CS signals are high. A high-to-low transition on the SCP1_CS line defines an SPI Start condition. A low-to-high transition on the SCP1_CS line defines an SPI Stop condition. Start and Stop conditions are always generated by the Master. The bus is considered to be busy after the Start condition. The bus is considered to be free again following the Stop condition.
SPI Port CS4953x4/CS4970x4 System Designer’s Guide SPI START: SCP1_CS (LOW) WRITE ADDRESS BYTE 0x80 WRITE 4 DATA BYTES Y MORE DATA? N SCP1_BSY (LOW)? N Y SPI STOP: SCP1_CS (HIGH) Figure 2-3. SPI Write Flow Diagram 2.4.3.2 SPI Write Protocol 1. A SPI transfer is initiated when the chip select SCP1_CS is driven low. SCP1_CS driven low indicates that CS4953x4/CS4970x4 is in SPI Slave mode. 2. This is followed by a 7-bit address and the read/write bit set low for a write.
SPI Port CS4953x4/CS4970x4 System Designer’s Guide bytes of any message length, so long as the correct hardware protocol is followed. The example shown in this section can be generalized to fit any SPI read situation. The flow diagram shown in Figure 2-4, illustrates the sequence of events that define the SPI read protocol. The Serial SPI read protocol is described in Section 2.4.3.4..
SPI Port CS4953x4/CS4970x4 System Designer’s Guide 5. If SCP1_IRQ is still low after 4 bytes, then proceed to Step 4 and read another 4 bytes out of the CS4953x4/CS4970x4 Slave. 6. If SCP1_IRQ is high, the SCP1_CS line of CS4953x4/CS4970x4 should be driven high to end the read transaction. 2-7 Copyright 2013 Cirrus Logic, Inc.
DS810UM6 SCP1_CS SCP1_MOSI 7-bit Address R /W SCP1_CLK Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) Figure 2-5. Sample Waveform for SPI Write Functional Timing SCP1_CS SCP1_MOSI SCP1_MISO 7-bit Address R /W Copyright 2013 Cirrus Logic, Inc SCP1_CLK Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) SCP1_IRQ Figure 2-6. Sample Waveform for SPI Read Functional Timing 1.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.4.3.5 SCP1_IRQ Behavior The SCP1_IRQ signal is not part of the SPI protocol, but is provided so that the Slave can signal that it has data to be read. A high-to-low transition on SCP1_IRQ indicates to the Master that the Slave has data to be read. When a Master detects a high-to-low transition on SCP1_IRQ, it should send a Start condition and begin reading data from the Slave.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.5.1 I2C System Bus Description Devices can be considered Masters or Slaves when performing data transfers. A Master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device addressed by the initiator is considered a Slave. The CS4953x4/CS4970x4 has two serial ports.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide Table 2-2. Serial Control Port 1 I2C Signals (Continued) LQFP-144 Pin # LQFP-128 Pin # Pin Type Serial Control Port 1 Input Busy, Output, Active Low This pin is driven low when the control port’s receive buffer is full. Internal Buffer is 4 bytes (1 DSP Word) deep. 102 128 Open Drain SCP2_CS SPI Chip Select, Active Low In serial SPI Slave mode, this pin is used as the active-low chip-select input signal.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide the CS4953x4/CS4970x4 is 1000000b (0x80). The R/W bit is used to notify the Slave if the current transaction is for the Master to write data to the Slave (R/W = 0) or read data from the Slave (R/W = 1). After the Master has sent the address byte, the Master releases the SCP1_SDA line. If the Slave received the address byte, it will drive the SCP1_SDA line low to acknowledge (ACK) to the Master that the byte was received.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide Start SCP1_CLK SCP1_SDA A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Data Byte ACK Write M S M S Read M S S M ACK Data Byte NACK S M S S S M Start SCP1_CLK SCP1_SDA A[6] A[5] A[4] A[3] A[2] Write M Read M A[1] A[0] R/W M = Master Drives SDA S = Slave Drives SDA Figure 2-11.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide Stop SCP1_CLK SCP1_SDA Data Byte ACK Write M S M Read S M M Stop SCP1_CLK SCP1_SDA Data Byte NACK Write M S M M M S M = Master Drives SDA S = Slave Drives SDA Read Figure 2-13.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.5.3.2 Performing a Serial I2C Write Information provided in this section is intended as a functional description indicating how to use the configured serial control port to perform a I2C write from an external device (Master) to the CS4953x4/ CS4970x4 DSP (Slave). The system designer must ensure that all timing constraints of the I2C write cycle are met (see the CS4953x4/CS4970x4 datasheet for timing specifications).
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.5.3.3 I2C Write Protocol 1. An I2C transfer is initiated with an I2C start condition which is defined as the data (SCP1_SDA) line falling while the clock (SCP1_CLK) is held high. 2. This is followed by a 7-bit address and the read/write bit held low for a write. So, the Master should send 0x80. The 0x80 byte represents the 7-bit I2C address 1000000b, and the least significant bit set to ‘0’, designates a write. 3.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide START N SCP1_IRQ (LOW)? Y SEND I2C START: DRIVE SCP1_SDA LOW WHILE SCP1_CLK IS HIGH WRITE ADDRESS BYTE 0x81 N EXIT (ERROR) SCP1_SDA == ACK? Y READ DATA BYTE SEND ACK BYTES READ = 4? N Y SCP1_IRQ LOW? Y N SEND NACK SEND I2C STOP: DRIVE SCP1_SDA HIGH WHILE SCP1_CLK IS HIGH Figure 2-15. I2C Read Flow Diagram 2-17 Copyright 2013 Cirrus Logic, Inc.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.5.3.5 I2C Read Procedure 1. An I2C read transaction is initiated by CS4953x4/CS4970x4 driving SCP1_IRQ low, signaling that it has data to be read. 2. The Master responds by sending an I2C Start condition which is SCP1_SDA going low while SCP1_CLK is held high. 3. This is followed by a 7-bit address and the read/write bit set high for a read. So, the Master should send 0x81.
Stop M S M Data Byte 1 S M Data Byte 0 (LSB) AC K S Data Byte 2 AC K M Data Byte 3 (MSB) AC K 7-bit Address AC K SCP1_SDA R /W AC K DS810UM6 Start SCP1_CLK S M S M Figure 2-16. Sample Waveform for I2C Write Functional TIming Note: The I2C Slave is always responsible for driving the ACK for the address byte.
I2C Port CS4953x4/CS4970x4 System Designer’s Guide 2.5.3.6 SCP1_IRQ Behavior Once the BOOT_ASSIST_A (.ULD file) has been downloaded in accordance to Steps 1 through 8 in Section 2.3.1. or Steps 1 through 8 in Section 2.3.2., the SCP1_IRQ pin is functionally enabled. The SCP1_IRQ signal is not part of the I2C protocol, but is provided so that the Slave can signal that it has data to be read. A high-to-low transition on SCP1_IRQ indicates to the Master that the Slave has data to be read.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Chapter 3 Audio Input Interfaces 3.1 Introduction CS4953x4/CS4970x4 support a wide variety of audio data formats through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. This data sheet presents most of the modes available with the CS4953x4/CS4970x4 hardware.
Digital Audio Input Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 3-1. Digital Audio Input Port (Continued) Pin Name Pin Description LQFP-144 Pin # LQFP-128 Pin # Pin Type DAI1_DATA0 PCM or Compressed Audio Input Data 0 PCM Audio Input Data 0 Serial data input that can accept PCM audio data that is synchronous to DAI_SCLK1/DAI_LRCLK1 or DAO1_SCLK/DAO1_LRCLK..
Digital Audio Input Port Description CS4953x4/CS4970x4 System Designer’s Guide Figure 3-1. DAI Port Block Diagram Currently supported are 4 lines of linear PCM input (DAI_DATA[3:0]) and 1 line of compressed audio or linear PCM (DAI_DATA4). These two inputs can have their own clock domains. The firmware currently available can operate on only one of these inputs at a time, providing for compressed data decode, stereo PCM processing, or multichannel PCM processing.
DAI Hardware Configuration CS4953x4/CS4970x4 System Designer’s Guide the right subframe is presented when DAIn_LRCLK is low. The left-justified format can also be programmed for data to be valid on the falling edge of DAIn_SCLK. L e ft C h a n n e l DAIn_LRCLK R ig h t C h a n n el DAIn_SCLK DAIn_DATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 3-2. Left-justified Format (Rising Edge Valid SCLK) 3.
DAI Hardware Configuration CS4953x4/CS4970x4 System Designer’s Guide . Table 3-3.
DAI Hardware Configuration CS4953x4/CS4970x4 System Designer’s Guide Table 3-4. Input SCLK Polarity Configuration (Input Parameter B) (Continued) B Value 1 SCLK Polarity (Both DAI and CDI Port) Hex Message Data Clocked in on SCLK Falling Edge Starting from DAI_D0 to DAI_D4: 0x81400020 0x00200000 0x81400021 0x00200000 0x81400022 0x00200000 0x81400023 0x00200000 0x81400024 0x00200000 . Table 3-5.
Digital Audio Input Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 3-6. Input DAI Mode Configuration (Input Parameter D) (Continued) D Value Description HEX Message 4 DAI1_LRCLK/SCLK - Slave Compressed Data on DAI_D0 and DAI_D0 to DAI_D4 enabled 0x81000025 0X0000D11F 3.4 Digital Audio Input Port Description CS4953x4/CS4970x4 is capable of accepting DSD audio data directly. DSD data differs from PCM in that audio is provided as a contiguous stream of 1’s and 0’s on a single line.
Digital Audio Input Port Description CS4953x4/CS4970x4 System Designer’s Guide DSD0 DSD_DATA0 DSD1 DMA to Peripheral Bus DSD_DATA1 DSD2 DSD_DATA2 DSD3 DSD_CLK DSD_DATA3 DSD4 DSD_DATA4 DSD5 DSD_DATA5 Figure 3-3. DSD Port Block Diagram §§ 3-8 Copyright 2013 Cirrus Logic, Inc.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Chapter 4 Audio Output Interface 4.1 Introduction The CS4953x4/CS4970x4 has two output ports - Digital Audio Output port 1 & 2 (DAO1 & DAO2). Each port can output 8 channels of up to 32-bit PCM data. The Digital Audio Output ports are both implemented with a modified 3-wire Inter-IC Sound (I2S) interface along with an oversampling Master clock (MCLK).
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide DAO1_SCLK is the bit clock used to clock data out on DAO1_DATA[3:0]. DAO1_LRCLK is the data framing clock whose frequency is equal to the sampling frequency for the DAO1 data outputs. DAO1_DATA[3:0] are the data outputs and are typically configured for outputting two channels of I2S or left-justified PCM data. DAO1_DATA0 may also be configured to provide output for four or six channels of PCM data.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide 4.2.2 Supported DAO Functional Blocks As mentioned earlier in the previous section, two DAO ports, DAO1_DATA3 and DAO2_DATA3, are unique in that they are designed to serve as either an output for I2S or left-justified PCM data or as S/PDIF transmitters (XMTA and XMTB).
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide 4.2.3.3 One-line Data Mode Format (Multichannel) The CS4953x4/CS4970x4 is capable of multiplexing all digital audio outputs on one line, as illustrated in Figure 4-4. This mode is available only through special request. Please contact your local Cirrus representative for further details.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-2 shows values and messages for DAO output clock mode configuration parameters. Table 4-2.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-4.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-4.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-5 shows values and messages for the data format configuration parameters. Table 4-5.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-6 shows values and messages for the DAO_LRCLK polarity configuration parameter. Table 4-6.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide To summarize the XMTA/XMITB S/PDIF output pins can be configured as: • I2S output - Default • S/PDIF Transmitter - Sent configuration from Table 4-10 • DSP Bypass - Send configuration from Table 4-11 The DSP Bypass configuration is typically used to route a S/PDIF stream from input to the output for recording applications or as a PCM bypass for dual-zone applications.
Digital Audio Output Port Description CS4953x4/CS4970x4 System Designer’s Guide Table 4-11. DSP Bypass Configuration DAO_SCLK Polarity Route XMTA_IN to DAO1_DATA3/XMTA and XMTB_IN to DAO2_DATA3/XMTB Route XMTA_IN to DAO1_DATA3/XMTA Route XMTB_IN to DAO2_DATA3/XMTB Disable DSP Bypass Hex Message 0x81000052 0x0000001B 0x81000052 0x00000013 0x81000052 0x0000000b 0x81000052 0x00000003 §§ 4-11 Copyright 2013 Cirrus Logic, Inc.
SDRAM Controller CS4953x4/CS4970x4 System Designer’s Guide Chapter 5 External Memory Interfaces 5.1 SDRAM Controller Products in the CS4953x4/CS4970x4 family that use a 144-pin package support a glueless external SDRAM interface to extend the data and/or program memory of the DSP during runtime. The CS4953x4/ CS4970x4 SDRAM controller provides two-port access to X, Y, and P memory space, a four-word read buffer, and a double-buffered four-word write buffer.
SDRAM Controller CS4953x4/CS4970x4 System Designer’s Guide 5.1.1 SDRAM Controller Interface The physical interface of the SDRAM controller consists of 16 data pins (SD_DATA[15:0]), 13 address pins (SD_ADDR[12:0]), 2 bank address pins (SD_BA[1:0]), and 9 control pins (SD_CS, SD_WE, SD_DQM1, SD_DQM0, SD_CAS, SD_RAS, SD_CLKOUT, SD_CLKIN, SD_CLKEN). SD_CS is the SDRAM chip select pin. The address and data pins are shared with the Flash interface.
SDRAM Controller CS4953x4/CS4970x4 System Designer’s Guide Table 5-1.
SDRAM Controller CS4953x4/CS4970x4 System Designer’s Guide Table 5-2.
SDRAM Controller CS4953x4/CS4970x4 System Designer’s Guide Table 5-2. SDRAM Interface Parameters (Continued) Mnemonic DynamictAPR Configure the last data out to active command time. Bit 31:4 = 0 = Reserved Bit 3:0 = Tapr, where: 0x0 to 0xE = (n + 1) DSP clk cycles. 0xF = 16 DSP clk cycles. DynamictDAL Configure the data-in to active command time. Bit 31:4 = 0 = Reserved Bit 3:0 = Tdal, where: 0x0 to 0xE = (n + 1) DSP clk cycles. 0xF = 16 DSP clk cycles.
SPI Flash Interface CS4953x4/CS4970x4 System Designer’s Guide Table 5-2. SDRAM Interface Parameters (Continued) Mnemonic Hex Message DynamictRRD Configure the active bank A to active bank B latency Bit 31:4 = 0 = Reserved Bit 3:0 = Trrd, where: 0x8100006B 0xhhhhhhhh Default 0x00000001 0x0 to 0xE = (n + 1) DSP clk cycles. 0xF= 16 DSP clk cycles. Example: Trrd = 15 nS, HCLK = 150 MHz Trrd = 15 nS * 150 MHz - 1= 2.25 - 1 = 0x2 DynamictMRD Configure the load mode register to active command time.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Chapter 6 System Design Requirements for SPDIF and HDMI™ Technology Interfaces 6.1 Introduction This chapter describes system design requirements when designing SPDIF and HDMI™ technologyinterfaces to the CS4953x4/CS4970x4 DSP. 6.1.1 Designing a SPDIF Input Interface The default input source state of the CS4953x4/CS4970x4 DSP is SPDIF with Autodetect. This setting is configurable in the flash_image.
Introduction CS4953x4/CS4970x4 System Designer’s Guide 6.1.2.2 Decoding Stream Types Over HDMI When decoding audio streams over HDMI, follow these practices: • In case of Multichannel PCM input over HDMI, specific AC3 decoder modes are used, that is, those modes specifically dedicated to Multichannel PCM inputs over HDMI. Refer to the sample flash_image.xml file, which is automatically installed when dspcondenser.exe is installed. Do not change the decoder mode when PCM over HDMI is detected.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Chapter 7 Overview of Common Firmware Modules 7.1 Introduction The purpose of this chapter is to serve as an introduction to firmware operation on the CS4953x4/ CS4970x4 DSP This chapter explains the general framework of operation on the CS4953x4/CS4970x4. • New boot code now boots off the customer’s SPI Flash device and allows the CS4953x4/CS4970x4 DSP chips to manage all boot tasks.
Firmware Messaging CS4953x4/CS4970x4 System Designer’s Guide The overlay architecture thus imposes limits on the types of concurrent firmware features (or modules) are available. The DSP Condenser tool set helps system designers understand and work within the concurrency limitations imposed by the firmware architecture. 7.3 Firmware Messaging While using the CS4953x4/CS4970x4 it is necessary to communicate with the DSP in order to control or monitor the various downloaded firmware modules.
Firmware Messaging CS4953x4/CS4970x4 System Designer’s Guide Write Data Word: 31 30 29 28 27 26 15 14 13 12 11 10 25 24 23 22 Data [31:0] 9 8 7 6 21 20 19 18 17 16 5 4 3 2 1 0 Options for Bits 23:22 23 22 Command 0 0 Write - current value overwritten 0 1 Write - new value OR’d with current value 1 0 Write - new value AND’d with current value 7.3.3 Solicited Read A solicited read can be thought of as a request to read the contents of a specific register.
Firmware Messaging CS4953x4/CS4970x4 System Designer’s Guide The 8-byte unsolicited read messages from the CS4953x4/CS4970x4 consist of a 4-byte read command word which defines the type of unsolicited message and an associated 4-byte data word that contains more information describing a system condition. The host senses that an unsolicited message is ready to be read because the IRQ pin for the port being used goes low (SCP1_IRQ or PCP_IRQ).
Firmware Messaging CS4953x4/CS4970x4 System Designer’s Guide Table 7-1. DSP_AUTODETECT_MSG Messages Bit Number Bit 31 Description Decodable_Stream_Flag = 0/1 = This stream is not/is decode-able by the application. Bit 5 Non_IEC61937_Stream_Flag= 1/0 = This stream is not/is IEC61937 compressed data. If Non_IEC61937_Stream_Flag=1 Non_IEC61937 Stream Descriptor.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide Table 7-2.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide AND Command = 0xEF80HHHH 0xhhhhhhhh Read Request Command = 0xEFCnHHHH Read Response Message = 0x6FC0HHHH 0xhhhhhhhh n = number of words – 1 (bits [20..16]) 0xHHHH = Index 0xhhhhhhhh = Data Value Table 7-3. Microcontroller Interface API Index 0x0000 Variable Description DSP_BOOT Bit 9 = Reserved Whenever a non-zero value is written to this register, the DSP manager firmware begins the specified configuration change.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide Table 7-4. DSP_CFG_xxx Firmware Configuration Registers (Continued) Index 0x0005 Variable DSP_CFG_OUTPUT_FS Description Output sample rate Bits 3:0 Sample Rate 0x0 = 48 KHz 0x1 = 44.1 KHz 0x2 = 32 KHz 0x3 = reserved 0x4 = 96 KHz 0x5 = 88.2 KHz 0x6 = 64 KHz 0x7 = reserved 0x8 = 24 KHz 0x9 = 22.05 KHz 0xA = 16 KHz 0xB = reserved 0xC = 192 KHz 0xD = 176.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide Table 7-4. DSP_CFG_xxx Firmware Configuration Registers (Continued) Index 0x0009 Variable DSP_CFG_VIRTUALIZER Description Bit 31:16 = VIRTUALIZER MODE 0x00 = MODE0. 0x01 = MODE1 0x02 = MODE2 0x03 = MODE3 0x04 = MODE4 Bit 15:0 = VIRTUALIZER ID 0x00 = none Other values determined by enumeration type created by flash image tool (Flasher).
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide Table 7-4.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide x= ppm mode defined for the first module ID (Module 1as defined in DSP_CFG_PPM_MODE1 in Table 7-4) in "ppm modes" section in the flash_image. xml file. w= ppm mode defined for the second module ID (Module 2 as defined in DSP_CFG_PPM_MODE1 in Table 7-4) in "ppm modes" section in the flash_image. xml file.
CS4953x4/CS4970x4 DSP Manager API Description CS4953x4/CS4970x4 System Designer’s Guide ucmd ef000007000m00dd # Set decoder (Required only when # switching Multichannel Analog Input # source.) ucmd ef0000130000xxxx # Set DSP_CFG_MCLK_FACTOR ucmd Ef00000000000001# Change to new configuration Where dd= decoder uld id capable of PCM decoding, m= decoder mode of the uld specified by 'dd'. Set m=0 and dd=00 to use the PCM decoder in OS.
Legacy API Still in Use CS4953x4/CS4970x4 System Designer’s Guide Table 7-5. Firmware Status Registers (Continued) Index Variable Description 0x00021 DSP_AUTODETECT_MSG Read Only Refer to Section 7.3.7 for more information. There are times when the DSP needs to inform the host of certain changes during its operation. For example, the DSP sending a message to the host indicating that the input stream has changed from Dolby Digital to DTS.
Legacy API Still in Use CS4953x4/CS4970x4 System Designer’s Guide Table 7-6. Legacy Audio Manager Index Variable Description 0x00000000-0x7FFFFFFF (-dB to +24 dB). Overall System Gain. Signed value 0x0000 GAIN with decimal point to the right of bit 27 (5.27 format). Range is zero to (16-2-27). Negative values can be used to invert the phase of all the outputs.
Legacy API Still in Use CS4953x4/CS4970x4 System Designer’s Guide Table 7-6. Legacy Audio Manager (Continued) Index 0x000C Variable CHAN_LFE3_TRIM Description 0x00000000 – 0x80000000 (0.0 to 1.0) Volume trim for LFE3 Channel Default* = 0x80000000† 0x000D 0x000E Reserved CHAN_Lt_TRIM 0x00000000 – 0x80000000 (0.0 to 1.0) Volume trim for Left DualZone Channel Default* = 0x80000000† 0x000F CHAN_Rt_TRIM 0x00000000 – 0x80000000 (0.0 to 1.
OS Firmware Module CS4953x4/CS4970x4 System Designer’s Guide Table 7-6. Legacy Audio Manager (Continued) Index 0x001A Variable DAO2_CHAN_0_REMAP Description Selects which internal channel (L, C, R, etc) is routed to DAO2 channel 0. A single internal channel may be mapped to multiple outputs. Default* = 0x0000000c (Left DualZone Channel Audio Data) 0x001B DAO2_CHAN_1_REMAP Selects which internal channel (L, C, R, etc) is routed to DAO2 channel 1.
OS Firmware Module CS4953x4/CS4970x4 System Designer’s Guide A. Variable is valid in DSPA OS B. Variable is valid in DSPB OS Table 7-7. OS Module Variables Index Variable A B Description Bit [31:0]: Number of samples (Left+Right) of silence upon which the DSP will declare Silence while having detected and currently playing PCM (Autodetect is enabled). 0x0008 PCM_AUTODETECT_ SILENCE_THRESHOLD X Note: Valid for all decoders when configured for PCM passthrough and auto switch.
Overview CS4953x4/CS4970x4 System Designer’s Guide Chapter 8 DSP Condenser 8.1 Overview Cirrus Logic provides the customer with the DSP Condenser application to implement the design capabilities described in Section P.1. The DSP Condenser application has the following features: • Customer specifies the DSP features such as the decoding modules to be used in the customer application.
Development Flow CS4953x4/CS4970x4 System Designer’s Guide In addition to tools supporting this development flow, the Condenser tool set includes sample microcontroller code, written in C language, which demonstrates how the microcontroller should control the DSP in the final design. Using this high-level tool set and methodology brings the system designer the following advantages: • DSP can directly access flash image, making firmware re-configuration faster and requiring less micro-controller effort.
Development Flow CS4953x4/CS4970x4 System Designer’s Guide for any given stream type, you can specify it now. You can always come back and change these settings later. e. Specify a reasonable Power-up state for your system design. f. Save the project. 5. Use the Build/Create flash image command in the wizard to actually create your first flash image. This is just a test of the build process - the image produced is not the final image. 6.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3 Elements of a Project The contents of a project are represented in the DSP Condenser Wizard GUI using “Master–Details” arrangement. This arangement consists of a tree of project elements (Master) on the left side of the GUI window and a set of properties (Details), displayed on the right, which vary according to the selection in the master.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide COM mode — Selects the serial communication protocol (SPI or I2C). 8.3.2 Search paths Page The Search paths page is used to define the search paths for specified ULDs and CFGs. The search is performed first under subdirectories named for the supported versions (listed in the General page), then directly in the specified directories. The search is performed in the order in which the paths are specified in the list. Figure 8-3.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.3 Audio sources Page The Audio sources page contains a list of all possible sources of audio presented to the DSP. Each audio source selected must have one or more .cfg files specified that contain the appropriate configuration messages so that the firmware OS can properly configure the DSP for receiving audio from that source. Figure 8-4.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.4 Sample rates Page The Sample rates page defines all the necessary hardware configurations to support various input and output sample rates. Figure 8-5.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.5 Firmware components Page The Firmware components page includes all of the firmware components (also referred to as "overlays" or ULDs) that are to be supported by the system being designed. This includes all decoders, matrix processors, virtualizers, and post processors grouped by category. Figure 8-6.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide Mode name — Customized name for selected snapshot (this name is used later throughout the GUI). This is also incorporated in the output .h file produced, as part of an enum that can be used by MCU code to specify the index. 8.3.6 PPM modes Page The PPM modes page defines which CFGs are necessary, depending on what mode is selected.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.7 Stream types Page The Stream types page contains a list of possible stream types. When autodetect occurs, the concurrency mode attached with the stream type is automatically loaded by the DSP. All modules and modes defined in the concurrency mode are loaded when a particular associated stream type is detected. Concurrency mode is the combination of firmware modules active at any one point in time. Figure 8-8.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.8 Power-up state Page The Power-up state page is used to define the default DSP state at power-up. This page defines initial modules (and their modes) to be loaded immediately after master boot. Figure 8-9.
Elements of a Project CS4953x4/CS4970x4 System Designer’s Guide 8.3.9 WAV update Page For easy deployment to systems in the field, a flash image update file can be created. The field upgrade SPI Flash image is created using the flash_to_wav utility, and contains multiple data structures, ULDs, and configuration message sets. The flash update image is formatted as a .wav file. The first part of the file is the .wav header. The data payload of the .
Creating a Condenser Project using a Model CS4953x4/CS4970x4 System Designer’s Guide 8.4 Creating a Condenser Project using a Model 8.4.1 Using the Wizard to Create a Project 1. Install the DSPcondenser.exe and the required firmware modules into the cs4953x_eval_kit install directory (Eg: C:\CirrusDSP). 2. Open dspcondenser wizard from the Start Menu CirusDSP.c . 3. To create a new project, Click on File New project. 4. Type a suitable project name. Choose the appropriate model.
Creating a Condenser Project using a Model CS4953x4/CS4970x4 System Designer’s Guide Click OK and the main screen of the new project window should appear as below.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide Click on Build->Create Flash Image The build log window will open displaying all the files (*.uld, *.cfg etc) listed in the project (underlying xml file) and also display if the image creation process was successful or not.. If there is a failure, scrolling through this log will give the error messages. The log will mention any missing uld or .cfg files. 8.5 Creating a Flash Image 8.5.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide 8.5.2 What Does the Image Contain? When the DSP operating system is running from a DSP Condenser project, it considers the flash attached to the DSP to be organized as shown: mCU Scratchpad Area DSP Scratchpad Area flash.img DSP Firmware and Config Files 0x0000 DSP Master Boot Code egg.img Figure 8-11.
Using DSP Condenser CS4953x4/CS4970x4 System Designer’s Guide 8.6 Using DSP Condenser 8.6.1 How to use DSP Composer with DSP Condenser Part of the goal of DSP Condenser is to allow Cirrus customers to specify as many firmware parameters at design time as is reasonable for their design. These design-time parameters can then be stored in the Flash image and downloaded as “modes” using the DSP Manager API, significantly reducing host-to-DSP communications requirements.
Using DSP Condenser CS4953x4/CS4970x4 System Designer’s Guide Figure 8-12. DSP Composer Sample Project, “WhizBang Model” Directory Structure: 8.6.1.2 Creating Projects A total DSP Condenser system design includes all of the firmware components (also referred to as “overlays” or ULDs) that are to be supported by the system under design.
Using DSP Condenser CS4953x4/CS4970x4 System Designer’s Guide Cirrus Logic recommends that each project be used to define settings for only one overlay, even though this means that more projects will be required. Such a separation makes it easier to separate out the effects of one component’s settings during listening/testing of the project. 8.6.2 Capturing Snapshots DSP Composer “snapshots” are sets of firmware module parameter settings, captured in DSP Composer using the Tools/Snapshots menu item.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide Figure 8-14. Sample Deliverables Directory Struction When DSP Composer generates deliverables, the configuration parameters (.cfg file) for each firmware component is saved into a separate file, with all .cfg files for a specific snapshot saved into a directory named for the snapshot. These individual .cfg files will later be used by other DSP Condenser tools to be incorporated into the Flash image.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide Figure 8-15. Blank SPI Flash Format 8.7.1.1 Master Boot Image (egg.img) The Master Boot Image, which is created by the DSP condenser tool, is customer system-specific. The Master Boot image is located in a locked area of SPI Flash, and must start at start at location 0x0000. The area designated for the Master Boot image is not updated during Field Flash updates. See Section 8.7.1.2. for more information.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide Note: This area of Flash may be destroyed when a Flash image is updated in the field, thereby losing any room calibration values. However, it is intended that this space be separated from the rest of the Flash image as much as possible, so that it may be preserved between Flash updates. 8.7.1.4 Microcontroller Unit (MCU) Scratchpad An area of Flash reserved for MCU usage.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide 8.7.2.1 Using the DSP Condenser Wizard to Create a Serial Flash Image To use the DSP Condenser wizard, follow these steps: 1. Install the DSPcondenser.exe and the required firmware modules into the cs4953x_eval_kit install directory (e.g.,:C:\CirrusDSP) 2. Open DSP Condenser wizard from the Start MenuCirrusDSP 3. To create a new project, Click on FileNew project. 4. Type a suitable project name. Choose the appropriate template.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide 6. At this point, the user can choose to build a project in one of two ways: A. Using one of the templates described in Step 4 without change b. Modifying the selected template as described in Section 7.4.2.1. 7. Click on BuildCreate Flash Image 8. The build log window will open as shown in Figure 8-18 displaying all the files (*.uld, *.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide 13. To program the serial Flash connected to the DSP, the egg.img, flash.img may be copied to: C:\Cirrus DSP\CS4953x\apps\\sd\flash Note: can be "crd49500" or "ck49x_4953x4" 8.7.2.2 Making Snapshots of a Change Perform the following steps to create several snapshots of changes in DSP Composer. 1. Make sure that the CS49x Board USB cable is plugged in. 2. Press the green Go button in DSP Composer.
Creating a Flash Image CS4953x4/CS4970x4 System Designer’s Guide 3. On the right, select CS497004_audio_manager_change as the Composer project. 4. Select audio_mgr_0db as mode 1, audio_mgr_minus10db as mode 2, and audio_mgr_plus10db as mode 3. 5. Save the project 6. On the DSP Condenser Wizard menu, select Build > Create Flash Image. Make sure that the flash image builds successfully. Scroll to the left to see the “Success” message. Close the log window after the flash image builds. 7.
DSP Response after Master Boot. CS4953x4/CS4970x4 System Designer’s Guide # DSP Flash status messages word 2: ef000020 word 3: 00008002 4. Issue the commands directly to put the DSP in update mode, described in the DSP_CFG_AUDIO_SRC variable in Table 7-4, "DSP_CFG_xxx Firmware Configuration Registers" on page 7-7. This step is not necessary if flash.img is not already programmed. Ef00000000000100 Ef00000600000007 Ef00001300000100 Ef00000000000001 read status messages word 0: ef000020 word 1: 00008002 5.
Host Activity CS4953x4/CS4970x4 System Designer’s Guide '81' correspond to the autodetection messages/response. For a description of autodetect messages, see Section 7.3.7 “DSP_AUTODETECT_MSG”on page 7-4. Figure 8-21 shows the autodetect message for silence. 8.9 Host Activity The host carries out the following activities after a successful boot. 1. Flush the DSP message buffer by reading all outstanding messages. 2.
Host Activity CS4953x4/CS4970x4 System Designer’s Guide Master Boot Host Reads all unsolicited messages, including: --Boot message --Autodetect message --ACCN message (if not silence/PCM) Host Sets System to Mute Host Reads all unsolicited messages, including: --Autodetect message --ACCN message (if not silence/PCM) No Success? Yes See Note below this flow chart.
DSP Condenser Runtime Application CS4953x4/CS4970x4 System Designer’s Guide Chapter 9 Using Runtime Condenser 9.1 DSP Condenser Runtime Application 9.1.1 Usage 9.1.1.1 Standard Launch The DSP Condenser Runtime is launched from the DSP Condenser application. The DSP Condenser application provides the .uld information to the runtime application. Use the following procedure. 1. Run DSP Condenser. 2. Create a flash DSP image using the DSP Condenser application as shown in Figure 9-1. Figure 9-1.
DSP Condenser Runtime Application CS4953x4/CS4970x4 System Designer’s Guide Figure 9-3. Program Flash on Board 5. Select “Run Runtime GUI (current project)” as shown in Figure 9-4. Figure 9-4. Run Runtime GUI 6. Select the DSP Manager API Input Source by changing the Source Combo Box as shown in Figure 9-5. Figure 9-5. DSP API Manager Input Source 9-2 Copyright 2013 Cirrus Logic, Inc.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide 7. Select the Board Input Source item from the Source Status group. This configuration should match what was set in Step 6. 8. Press “Connect to Board”. 9. Press “Refresh” in the DSP Manager API Group to see the current DSP Manager API State. 10. Change the appropriate combo boxes in the DSP Manager API Group. These controls turn red to indicate the values have changed. 11. Press “Apply”. Any values that have changed are sent to the DSP.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide 9.2.1.1 Connection to Board Button This connects/disconnects to a CDB49x board through the USB port. 9.2.1.2 Connection Status Led This shows if the DSP Condenser Runtime application is attached to a CDB49x board. 9.2.1.3 Use JP1 Checkbox1 Check the JP1 checkbox if a DSP board is connected to the JP1 header on the customer-designed board. 9.2.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide 9.2.2.4.2 Configuration File Commmand The configuration file command is the full path name of the configuration file sent down. The configuration file must have a *.cfg extension and be a valid Cirrus DSP Configuration file. After the enter key is pressed, the commands in the configuration file are sent to the DSP and shown in black in the “Log” window. 9.2.2.4.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide • DSP write • brd_cfg -w board 00 02 24 02 tx: 80000001 DSP read - rx: ef000020 9.2.4.2 Menu Items By right-clicking on the “Log” window, a menu is shown with the following options: • Save As–Save the log as a text file for later viewing. • Save As *.cfg–Save as a DSP configuration file. The configuration file includes all the writes since the last reset. • Copy–Copies the selection to the clipboard.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide 9.2.6 Source Status Group This group shows the current board configuration. When the connection is in JP1 mode, this group is disabled. Figure 9-11. DSP Condenser Runtime Source Status Group 9.2.6.1 Manual Refresh Button The “Manual Refresh” button reads the DSP board’s source configuration and updates the “Source Status” text fields. 9.2.6.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide “Compressed”, “Uncompressed”, and “Unconfigured”. • Mute–Status of mute in DAC. The possible values are “On”, “Off”, and “Unconfigured”. • HDMI Fs–This determines the DAI LRCLK frequency based on N, CTS values and/or the audio sampling frequency register. The possible values while in an HDMI Source mode are “Off”, “Video Passthru”, “I2S 1Fs”, “I2S 2Fs”, “I2S 4Fs”, and “I2S SPDIF”.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide Figure 9-13. DSP Manager API Group without Image Information 9.2.7.1 Source The source shows the value of the DSP_CFG_AUDIO_SRC Register. The possible options are determined by the flash image information. The values can be “SPDIF”, “SPDIF_NO_AUTOSWITCH”, “HDMI”, “HDMI_NO_AUTOSWITCH”, and “MULTICHANNEL”. 9.2.7.2 MCLK Factor The MCLK Factor shows the value of the DSP_CFG_MCLK_FACTOR Register.
Runtime GUI Current Project CS4953x4/CS4970x4 System Designer’s Guide 9.2.7.7 PPM The PPM reflects the value of the DSP_CFG_PPM Register. 9.2.7.8 PPM Mode List The PPM Mode Lists reflects the value of the DSP_PPM_MODE1-5 Registers. 9.2.7.9 Refresh Button After the user connects to the board, the user is able to push the “Refresh” button to refresh all of the values in the DSP Manager API group. All combo boxes/spinner controls in the DSP Manager API group whose value is red is reset to black. 9.2.7.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Appendix A FAQ A.1 Introduction Appendix A contains design tips in the familiar Question and Answer format. The issues discussed are workarounds and techniques perfected by Cirrus Logic internal designers and support staff to smooth the path of DSP system designers. A.2 List of Questions and Answers Q 1. I would like to create a custom flash image. How does one edit the Flash_image.xml file? A 1. View the sample flash_image.
List of Questions and Answers CS4953x4/CS4970x4 System Designer’s Guide Q 2.How do I create deliverables using DSP Composer? A 2.Create DSP Composer Deliverables using the following procedure: 1. Install the latest version of the DSP Condenser. This should contain the ‘flasher’ utility, sample DSP Composer projects (.cpa) files and a sample .xml file (flash _image.xml) . The flash_image.xml is an input to the flasher utility. 2. Install the latest version of the firmware modules. For example, ac3.exe, aac.
List of Questions and Answers CS4953x4/CS4970x4 System Designer’s Guide 5. Click on ‘Generate Deliverables’ in the ‘Tools’ menu for each of the .cpa files opened. All the generated deliverables must be saved under one parent directory. For example: C:\CirrusDSP\DSPCondenser\projects\sample_cirrus\deliverables. Refer to the DSP Composer manual for more details. Also, refer to Section 8.6.1.1, "Best Practices" on page 8-17 on suggested directory structure. §§ A-3 Copyright 2013 Cirrus Logic, Inc.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Appendix B Optional Features B.1 Introduction Appendix B describes optional features that are available to Cirrus Logic customers on request by contacting your Cirrus Logic FAE or represenative. This feature is not currently supported by the CS4953x4/CS4970x4 product firmware. B.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Appendix C Loading/Unloading Firmware Modules C.1 Introduction Appendix C describes how to load and unload various firmware modules in DSP Condenser. This occurs the host changes concurrency mode(s). See Section 7.4.2.1, “Using DSP Condenser to Change/Load Firmware Modules” on page 7-10 for more detailed information on loading and unloading firmware modules.
Introduction CS4953x4/CS4970x4 System Designer’s Guide C.1.2.1 Loading DTS-ES Decoder in Matrix Mode The host commands necessary to load DTS-ES in matrix mode are: UCMD UCMD UCMD UCMD Ef00000000000100 Ef000007000x00yy Ef000008000000zz #Loads DTS Neo6 required to load DTS ES Matrix Ef00000000000001 X= DTS_ES decoder mode with matrix ON, yy= dts_es uld id, zz = neo 6 uld id C.1.3 Dolby Digital® See the Cirrus Logic application note, AN246DA for a complete description of the Dolby Digital firmware module.
Introduction CS4953x4/CS4970x4 System Designer’s Guide UCMD Ef00000000000001 x= SGEN mode, yy= SGEN uld id C.1.5 Dolby Digital®PLus See the Cirrus Logic application note, AN304DA for a complete description of the Dolby Digital Plus firmware module. C.1.5.1 Loading Dolby Digital Plus for Stereo Output The host commands necessary to load Dolby Digital Plus for stereo output are UCMD UCMD UCMD UCMD Ef00000000000100 Ef000007000x00yy Ef00000B0000000z Ef00000000000001 x = DDplus mode for stereo output (Eg.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Note: When the downmix option is chosen (also reflected in the output mode), the program chosen from the input stream changes to the one with lower number of channels and the CHANNEL ASSIGNMENT field in the ACCN message reflects this change. The FORMAT INFO field of the ACCN message still displays all the available programs in the stream. C.1.6.
Introduction CS4953x4/CS4970x4 System Designer’s Guide C.1.8 Dolby Virtual Speaker® 2 See the Cirrus Logic application note, AN246MPL for a complete description of the Dolby Virtual Speaker 2 (DVS2) firmware module. C.1.8.1 Loading Dolby Virtual Speaker 2 The host commands necessary to load Dolby Virtual Speaker 2 are: UCMD Ef00000000000100 UCMD Ef000009000p000q UCMD Ef00000000000001 p = DVS2 mode, q= DVS2 uld id as per flash.h C.1.8.
Introduction CS4953x4/CS4970x4 System Designer’s Guide C.1.9.2 Loading Dolby Headphone 2 with Dolby ProLogic II The host commands necessary to load Dolby Headphone 2 along with Dolby ProLogic II are: UCMD UCMD UCMD UCMD Ef00000000000100 Ef000008000p000q Ef000009000r000s Ef00000000000001 p = PL2x_A mode, q = PL2x_A uld id as per flash.h r = DH2 mode, s = DH2 uld id as per flash.h C.1.9.
Introduction CS4953x4/CS4970x4 System Designer’s Guide C.1.11 DTS-HD™ Master Audio See the Cirrus Logic application note, AN304DD for a complete description of the DTS-HD™ Master Audio firmware module. C.1.11.1 Loading DTS-HD Master Audio for Stereo Downmix Output The host commands necessary to load DST-HD Master Audio for Stereo downmix output are: 1.
Introduction CS4953x4/CS4970x4 System Designer’s Guide Cirrus Logic recommends that apply_crossbar_b be used for dual zone output with Logic 7 and HD decoders. Also, use apply_crossbar_b for DTSHD-MA main downmix as well as dual zone downmix. C.1.13 Intelligent Room Calibration 2 (IRC2) See the Cirrus Logic application note, AN246PPJ for a complete description of the IRC2 firmware module. C.1.13.1 Configuring the DSP for IRC2 Follow these steps to configure the DSP for IRC2: 1.
Revision History CS4953x4/CS4970x4 System Designer’s Guide When writing to the serial flash, the first location should have the number of words, calculated based on the number of bands, number of channels, etc Example: 0x74000: 00000002 : d5000025 : 00200020 This example saves one coefficient. 5. Return to normal operation after writing the coefficients by performing a master boot. 6.
