Manual

CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752F1 23
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.17 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
(SD_CLKOUT = SD_CLKIN)
Parameter Symbol Min Typical Max Unit
SD_CLKIN high time
t
sdclkh
2.3 ——ns
SD_CLKIN low time
t
sdclkl
2.3 ——ns
SD_CLKOUT rise/fall time
t
sdclkrf
——1ns
SD_CLKOUT Frequency
——
150 — MHz
SD_CLKOUT duty cycle
—
45 — 55 %
SD_CLKOUT rising edge to signal valid
t
sdcmdv
——3.8 ns
Signal hold from SD_CLKOUT rising edge
t
sdcmdh
— 1.1 — ns
SD_CLKOUT rising edge to SD_DQMn valid
t
sddqv
— 3.8 — ns
SD_DQMn hold from SD_CLKOUT rising edge
t
sddqh
1.38 ——ns
SD_DATA valid setup to SD_CLKIN rising edge
t
sddsu
1.3 ——ns
SD_DATA valid hold to SD_CLKIN rising edge
t
sddh
2.1 ——ns
SD_CLKOUT rising edge to ADDRn valid
t
sdav
— 3.8 — ns
DAO_SCLK
DAO_LRCLK
DAO_Dx
t
daoslrts
t
daosclk
DAO_SCLK
DAO_LRCLK
t
daosstlr
t
daosdv
t
daosclk
DAO_Dx
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK