Manual

CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752F1 17
Figure 7. Parallel Control Port - Intel

Slave Mode Read Cycle
Delay between PCP_RD
then PCP_CS low or PCP_CS then
PCP_RD low
t
icdr
0——ns
Data valid after PCP_CS and PCP_RD low
t
idd
——18ns
PCP_CS and PCP_RD low for read
t
irpw
24 — — ns
Data hold time after PCP_CS or PCP_RD high
t
idhr
8——ns
Data high-Z after PCP_CS or PCP_RD high
t
idis
——18ns
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
read
1
t
ird
30 — — ns
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
write
1
t
irdtw
30 — — ns
PCP_RD rising to PCP_IRQ rising
t
irdirqhl
——12ns
Write
Delay between PCP_WR then PCP_CS low or PCP_CS then
PCP_WR
low
t
icdw
0——ns
Data setup before PCP_CS or PCP_WR high
t
idsu
8——ns
PCP_CS and PCP_WR low for write
t
iwpw
24 — — ns
Data hold after PCP_CS or PCP_WR high
t
idhw
8——ns
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
read
1
t
iwtrd
30 — — ns
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
write
1
t
iwd
30 — — ns
PCP_WR rising to PCP_BSY falling
t
iwrbsyl
— 2*DCLKP + 20 — ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_
BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
Parameter Symbol Min Typical Max Unit
PCP_A[3:0]
PCP_D[7:0]
t
ias
t
icdr
t
iah
t
idd
t
irpw
t
idhr
t
idis
t
ird
t
irdtw
PCP_CS#
PCP_WR#
PCP_RD#
PCP_IRQ#
t
irdirqh
LSP MSP