CS4954 CS4955 NTSC/PAL Digital Video Encoder Features Description z Six The CS4954/5 provides full conversion from digital video DACs providing simultaneous composite,S-video, and RGB or Component formats YCbCr or YUV to NTSC and PAL Composite, Y/C (S-video) and RGB, or YUV analog video. Input forYUV outputs mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU z Programmable DAC output currents for low R.BT656 with support for EAV/SAV codes. Video output impedance (37.
CS4954 CS4955 ORDERING INFORMATION Product CS4954 Description Package Pb-Free CS4955 NTSC/PAL Digital Video Encoder 48-TQFP Yes CDB4954/55 CS4954/55 Evaluation Board No 2 Grade Temp Range Container Commercial -40º to +85ºC - - Rail - Order# CS4954-CQZ CS4955-CQZ CDB4954A/55A DS278F6
CS4954 CS4955 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. 7. DS278F6 CHARACTERISTICS AND SPECIFICATIONS ........................................................................................6 AC & DC PARAMETRIC SPECIFICATIONS ............................................................................................6 RECOMMENDED Operating Conditions .......................................................................................................6 THERMAL CHARACTERISTICS ...............................
CS4954 CS4955 7.4.5 Green DAC ....................................................................................................................... 33 7.4.6 Blue DAC .......................................................................................................................... 33 7.4.7 DAC Useage Rules ........................................................................................................... 34 8. PROGRAMMING .....................................................................
CS4954 CS4955 LIST OF FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. 5 Video Pixel Data and Control Port Timing ..................................................................8 I²C Host Port Timing ................
CS4954 CS4955 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS AC & DC PARAMETRIC SPECIFICATIONS (AGND,DGND = 0 V, all voltages with respect to 0 V) Parameter Power Supply Symbol Min Max VAA/VDD Units -0.3 6.0 V Input Current Per Pin (Except Supply Pins) -10 10 mA Output Current Per Pin (Except Supply Pins) -50 +50 mA Analog Input Voltage -0.3 VAA + 0.3 V Digital Input Voltage -0.3 VDD + 0.
CS4954 CS4955 Parameter Symbol Min Typ VOL - - 0.4 V - -10 - +10 μA (Notes 1, 2, 3) IO 32.9 34.7 36.5 mA Low Level Output Voltage SDA pin only, lo = 6mA Output Leakage Current High-Z Digital Outputs Max Units Analog Outputs Full Scale Output Current CVBS/Y/C/R/G/B Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IO 8.22 8.68 9.13 mA LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IB 32.2 33.9 35.7 μA LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IB 8.04 8.48 8.
CS4954 CS4955 AC CHARACTERISTICS Parameter Symbol Min Typ Max Units Tch 14.82 18.52 22.58 ns Pixel Input and Control Port (Figure 1) Clock Pulse High Time Clock Pulse Low Time Tcl 14.82 18.52 22.58 ns Clock to Data Set-up Time Tisu 6 - - ns Clock to Data Hold Time Tih 0 - - ns Clock to Data Output Delay Toa - - 17 ns CLK Tisu Tch Tcl V[7:0] Tih HSYNC/VSYNC (Inputs) Toa HSYNC/VSYNC CB/FIELD(1)/INT (Outputs) Figure 1.
CS4954 CS4955 TIMING CHARACTERISTICS Parameter Symbol Min Typ Max Units 1000 kHz I²C Host Port Timing (Figure 2) SCL Frequency Fclk Clock Pulse High Time Tsph 0.1 μs Clock Pulse Low Time Tspl 0.7 μs Hold Time (Start Cond.) Tsh 100 ns Setup Time (Start Cond.) Tssu 100 ns Data Setup Time Tsds 50 ns Rise Time Tsr 1 μs Fall Time Tsf 0.3 μs Setup Time (Stop Cond.
CS4954 CS4955 TIMING CHARACTERISTICS(Continued) Parallel Host Port Timing (Figure 27, 28, 29) Symbol Min Typ Max Units Read Cycle Time Trd 60 - - ns Read Pulse Width Trpw 30 - - ns Address Setup Time Tas 3 - - ns Read Address Hold Time Trah 10 - - ns Read Data Access Time Trda - - 40 ns Read Data Hold Time Trdh 10 - 50 ns Write Recovery Time Twr 60 - - ns Twpw 40 - - ns Write Data Setup Time Twds 8 - - ns Write Data Hold Time Twdh 3 - - ns Wri
CS4954 CS4955 2. ADDITIONAL CS4954/5 FEATURES • Five programmable DAC output combinations, including YUV and second composite • Optional pseudo-progressive scan @ MPEG2 field rates • Stable color subcarrier for MPEG2 systems • General purpose input and output pins • Individual DAC power-down capability • On-chip color bar generator • Supports RS170A and ITU R.BT601 composite output timing • HSYNC and VSYNC output in ITU R.
CS4954 CS4955 The CS4954/5 is designed to function as a video timing master or video timing slave. In both Master and Slave Modes, all timing is sampled and asserted with the rising edge of the CLK pin. In most cases, the CS4954/5 will serve as the video timing master. HSYNC, VSYNC, and FIELD(1) are configured as outputs in Master Mode. HSYNC or FIELD can also be defined as a composite blanking output signal in Master Mode.
CS4954 CS4955 able gain amplifiers in which the chroma amplitude can be varied via the U_AMP and V_AMP 8-bit host addressable registers. The U and V chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. The chroma is then interpolated by a factor of two in order to operate the output DACs at twice the pixel rate.
CS4954 CS4955 DAC Pin # Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Y 48 Y Y Y CVBS_2 CVBS_2 C 47 C C C - - CVBS 44 CVBS_1 CVBS_1 CVBS_1 CVBS_1 CVBS_1 R 39 R Cr (V) - R Cr (V) G 40 G Y CVBS_2 G Y B 43 B Cb (U) - B Cb (U) Table 1. DAC configuration Modes the six DACs has its own associated DAC enable bit. In the Disable Mode, the 10-bit DACs source (or sink) zero current. When running the DACs with a low-impedance load, a minimum of three DACs must be powered down.
CS4954 CS4955 4.12 Teletext Services The CS4954/5 encodes the most common teletext formats, such as European Teletext, World Standard Teletext (PAL and NTSC), and North American Teletext (NABTS). Teletext data can be inserted in any of the TV lines (blanking lines as well as active lines). In addition the blanking lines can be individually allocated for Teletext instantiation. The input timing for teletext data is user programmable. See the section Teletext Services for further details.
CS4954 CS4955 NTSC 27MHz Clock Count PAL 27MHz Clock Count 1682 1683 1684 1685 1686 1702 1703 1704 1705 1706 ••• ••• 1716 1728 1 1 2 2 3 3 ••• ••• 128 128 129 129 ••• ••• 244 264 245 265 246 266 247 267 248 268 CLK HSYNC (input) V[7:0] (SYNC_DLY=0) Y ••• V[7:0] (SYNC_DLY=1) Cb Cr Y Cb active pixel #720 Y active pixel #719 Cr Y active pixel #1 horizontal blanking Y Cb active pixel #720 horizontal blanking Cr Y active pixel #2 Y active pixel #1 Cr active pixel #2 Figure
CS4954 CS4955 PROG_VS Register (0x0D). VSYNC can be delayed by thirteen lines or advanced by eighteen lines. (falling) edge of HSYNC if the PROG_HS Registers are set to default values. 5.2.3 Vertical Timing 5.2.
CS4954 CS4955 NTSC Vertical Timing (odd field) Line 3 4 5 6 7 8 9 10 267 268 269 270 271 3 4 5 6 7 314 315 316 317 318 HSYNC VSYNC FIELD NTSC Vertical Timing (even field) Line 264 265 266 HSYNC VSYNC FIELD PAL Vertical Timing (odd field) Line 265 1 2 HSYNC VSYNC FIELD PAL Vertical Timing (even field) Line 311 312 313 HSYNC VSYNC FIELD Figure 6. Vertical Timing VSYNC stays low for 2.5 line-times and transitions high with the beginning of line 315.
CS4954 CS4955 Analog Field 1 523 524 525 1 VSYNC Drops 2 3 4 5 6 7 8 9 10 22 Analog Field 2 261 262 263 264 265 266 Analog Field 3 523 524 525 1 267 268 269 270 271 272 284 285 VSYNC Drops 2 3 4 5 6 7 8 9 10 22 Analog Field 4 261 262 263 264 265 266 267 268 Burst begins with positive half-cycle 269 270 271 272 284 285 Burst begins with negative half-cycle Figure 7.
CS4954 CS4955 VSYNC Drops Analog Field 1 620 621 622 623 624 625 1 2 3 4 5 6 7 23 24 Analog Field 2 308 309 310 311 312 313 314 315 316 317 318 319 320 336 337 Analog Field 3 620 621 622 623 624 625 1 2 3 4 5 6 7 23 24 Analog Field 4 308 309 310 311 312 313 314 315 316 317 318 319 320 336 337 Analog Field 5 620 621 622 623 624 625 1 2 3 4 5 6 7 23 24 Analog Field 6 308 309 310 311 312 313 314 315 316 317 318 319 320
CS4954 CS4955 Start of VSYNC 262 263 1 2 3 4 Field 1 5 6 7 8 9 10 22 6 7 8 9 10 22 6 7 8 9 10 22 6 7 8 9 10 22 Field 2 261 262 1 2 3 4 5 Start of VSYNC 262 263 1 2 3 4 Field 3 5 Field 4 261 262 1 2 3 4 5 Burst begins with positive half-cycle Burst begins with negative half-cycle Burst phase = reference phase = 180 0 relative to B-Y Burst phase = reference phase = 180 0 relative to B-Y Figure 9.
CS4954 CS4955 VSYNC Drops Analog Field 1 309 310 311 312 313 1 2 3 4 5 6 7 23 24 2 3 4 5 6 7 23 24 2 3 4 5 6 7 23 24 2 3 4 5 6 7 23 24 Analog Field 2 308 309 310 311 312 1 Analog Field 3 309 310 311 312 313 1 Analog Field 4 308 309 310 311 312 1 Burst Phase = 135 degrees relative to U Burst Phase = 225 degrees relative to U Figure 10. PAL Video Non-Interlaced Progressive Scan Timing Composite Video ITU R.
CS4954 CS4955 System NTSC-M, NTSC-J Fsubcarrier Value (hex) 3.5795455 MHz 43E0F83E PAL-B, D, G, H, I, N 4.43361875 MHz 54131596 PAL-N (Argentina) 3.582056 MHz 43ED288D PAL-M 3.579611 MHz 43CDDFC7 Table 3. 5.7 Subcarrier Compensation Since the subcarrier is synthesized from CLK, the subcarrier frequency error will track the clock frequency error. If the input clock has a tolerance of 200 ppm then the resulting subcarrier will also have a tolerance of 200 ppm.
CS4954 CS4955 all 4 bytes to be inserted to the registers and then enables closed caption insertion and interrupts. As the closed caption interrupts occur, the host software responds by writing the next two bytes to be inserted to the correct control registers and then clears the interrupt and waits for the next field. 5.9 Programmable H-sync and V-sync It is possible in master mode to change the H-sync and V-sync times based on register settings.
CS4954 CS4955 TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at independently selectable lines for both TV fields. The internal insertion window for text is set to either 360, 296 or 288 teletext bits, depending on the selected teletext standard. The clock run-in is included in this window. Teletext in enabled by setting the TTX_EN bit to “1”.
CS4954 CS4955 order to maintain the strict timing requirements of the teletext standard. Table 5 shows how to program the TTXHS register for teletext instantiation into the analog signals for the various supported TV formats. TTXHS is the time between the leading edge of the HSYNC signal and the rising edge of the first TTXRQ signal and consists of multiples of 27 MHz clock cycles Note that with increasing values of TTXHS the time tTTX increases as well.
CS4954 CS4955 Color White Yellow Cyan Green Magenta Red Blue Black Cb 0 - 84 + 28 - 56 + 56 - 28 + 84 0 Cr 0 + 14 - 84 - 70 + 70 + 84 - 14 0 Y + 167 + 156 + 138 + 127 + 110 + 99 + 81 + 70 Table 6. Internal Color Bar Values (8-bit values, Cb/Cr are in twos complement format) 5.13 VBI encoding VBI (Vertical Blanking Interval) encoding is performed according to SMPTE RP 188 recommendations. In NTSC mode, lines 10 - 20 and lines 272 283 are used for the transmission of ancillary data.
CS4954 CS4955 tions of GPIO_DATA_REG when it detects register address 0×0A through the I²C interface. A detection of address 0×0A can happen in two ways. The first and most common way this will happen is when address 0×0A is written to the CS4954/5 via its I²C interface. The second method for detecting address 0×0A is implemented by accessing register address 0×09 through I²C.
CS4954 CS4955 6. FILTER RESPONSES 1.3 Mhz. filter passband response 1.3 Mhz. filter frequency response 0 -10 0 magnitude - dB magnitude - dB -20 -30 -40 -0.1 -0.2 -0.3 -50 -0.4 -60 -70 0 1 2 3 4 frequency (Hz) 5 6 -0.5 6 x 10 Figure 14. 1.3 MHz Chrominance low-pass filter transfer characteristic 0 2 4 6 frequency (Hz) 10 12 x 10 5 Figure 15. 1.3 MHz Chrominance low-pass filter transfer characterstic (passband) 650 Khz. filter passband response 650 Khz.
CS4954 CS4955 Luma Output Interpolation Filter Response at 27MHz full scale Chroma Output Interpolator Pass band 1 0 0.8 -5 Magnitude Response (dB) Magnitude Response (dB) 0.6 0.4 0.2 0 -0.2 -0.4 -10 -15 -20 -25 -30 -0.6 -35 -0.8 -1 -40 0 0.5 1 1.5 2 2.5 3 Frequency (MHz) 3.5 4 4.5 0 5 Figure 18. Chrominance output interpolation filter transfer characteristic (passband) 2 0 -5 Magnitude Response (dB) Magnitude Response (dB) 0 -0.5 -1 -1.5 -2 -25 -35 6 7 8 Figure 20.
CS4954 CS4955 RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) 0 0.5 -5 0 -10 Magnitude Response (dB) Magnitude Response (dB) RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) (-3 dB) 1 -0.5 -1 -1.5 -2 -20 -25 -30 -35 -2.5 -3 -15 -40 0 2 4 6 8 Frequency (MHz) 10 12 Figure 22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) -45 0 2 4 6 8 Frequency (MHz) 10 12 Figure 23.
CS4954 CS4955 7. 7.1 ANALOG Analog Timing All CS4954/5 analog timing and sequencing is derived from the 27 MHz clock input. The analog outputs are controlled internally by the video timing generator in conjunction with master and slave timing. Since the CS4954/5 is almost entirely a digital circuit, great care has been taken to guarantee analog timing and slew rate performance as specified in the NTSC and PAL analog specifications.
CS4954 CS4955 7.4.2 Chrominance DAC The C output pin is driven from a 10-bit 27 MHz current output DAC that internally receives the C or chrominance portion of the video signal (color only). The C DAC is designed to drive proper video levels into a 37.5 Ω load. Reference the detailed electrical section of this data sheet for the exact C digital to analog AC and DC performance data. The EN_C enable control register bit in Control Register 1 (0×05) is provided to enable or disable the chrominance DAC.
CS4954 CS4955 current flow from the output. To completely disable or for low power device operation, the blue DAC can be totally shut down via the B_PD control register bit in Control Register 4 (0×04). In this mode turn-on using the control register will not be instantaneous. Nominal Power supply 7.4.7 DAC Useage Rules If some of the 6 DACs are not used, it is strongly recommended to power them down (see CONTROL_4 register) in order to reduce the power dissipation.
CS4954 CS4955 must be tied to ground. PDAT [7:0] are available to be used for GPIO operation in I²C host interface mode. For 3.3 V operation it is necessary to have the appropriate level shifting for I²C signals. SDA SCL A 1-7 Start 8 Address R/W 9 ACK 8 1-7 Data 9 1-7 ACK 8 9 Data ACK P Stop Note: I²C transfers data always with MSB first, LSB last Figure 26. I²C Protocol 8.1.
CS4954 CS4955 Trd RD Trpw Trah PADR PDAT[7:0] Trdh Trda Tas Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle Twpw Twr WR Twac PADR PDAT[7:0] Tas Twds Twdh Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle 8.2 Register Description A set of internal registers are available for controlling the operation of the CS4954/5. The registers extend from internal address 0×00 through 0×5A. Table 9 shows a complete list of these registers and their internal addresses.
CS4954 CS4955 Address 0×09 0×0A 0×0B 0×0C 0×0D 0×0E 0×0F 0×10 0×11 0×12 0×13 0×14 0×15 0×16 0×17 0×18 0×19 0×1A 0×1B 0×1C 0×1D 0×1E 0×1F 0×20 0×21 0×22 0×23 0×24 0×25 0×26 0×27 0×28 0×29 0×2A 0×2B 0×2C 0×2D 0×2E 0×2F 0×30 0×31 0×32 0×33 Register Name gpio_ctrl_reg gpio_data_reg RESERVED RESERVED SYNC_0 SYNC_1 I²C_ADR SC_AMP SC_SYNTH0 SC_SYNTH1 SC_SYNTH2 SC_SYNTH3 HUE_LSB HUE_MSB SCH PHASE ADJUST CC_EN CC_21_1 CC_21_2 CC_284_1 CC_284_2 RESERVED WSS_REG_0 WSS_REG_1 WSS_REG_2 RESERVED CB_AMP CR_AMP Y_AMP R_AM
CS4954 CS4955 Address 0×34 0×35 - 0×59 0×5A 0×61 - 0×7F Register Name STATUS_0 RESERVED STATUS_1 RESERVED Type read only Default value read only 04h Table 9.
CS4954 CS4955 Bit Mnemonic 5 CH BW chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 MHz) 4 LPF ON chroma lpf on/off (0 = off, 1 = on) 3 RGB_BW 0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0) 2 FLD_POL Polarity of Field (0: odd field = 0,1: odd field = 1) 1 PED 0 CBCRSEL DS278F6 Function Pedestal offset (0: 0 IRE, 1: 7.
CS4954 CS4955 Control Register 2 Address Bit Number Bit Name Default Bit 0×02 CONTROL_2 7 6 Read/Write 5 OUTPUT FORMAT 0 0 0 Default Value = 00h 4 3 2 1 0 TTX WST TTX EN SYNC_DLY XTAL SC_EN 0 0 0 0 0 Mnemonic Function selects the output through the DACs 7:5 OUTPUT FORMAT 000 : rgb, s-video, composite1 (6 DACs) (default) 001 : yuv, s-video, composite1 (6 DACs) 010 : s-video, composite1, composite2, (4 DACs) 011 : rgb, composite1, composite2 (5 DACs) 100 : yuv, composite1
CS4954 CS4955 Control Register 3 0×03 Address Bit Number Bit Name Default CONTROL_3 7 6 Read/Write 5 4 RESERVED 0 Default Value = 00h 3 2 1 0 FD THR C1 FD THR C2 FD THR SV FD THR EN 0 0 0 0 0 CBAR 0 0 Bit Mnemonic Function 7:5 - 4 FD THR C1 feedthrough enabled for composite 1 output (0 = off, 1 = on) 3 FD THR C2 feedthrough enabled for composite 2 output (0 = off, 1 = on) 2 FD THR SV feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on) 1 FD THR_EN Enable (1
CS4954 CS4955 Control Register 5 0×05 Address CONTROL_5 Read/Write Default Value = 00h Bit Number Bit Name Default 7 6 5 4 3 2 1 0 RSVD LOW IMP EN COM EN L EN C EN R EN G EN B 0 0 0 0 0 0 0 0 Bit Mnemonic 7 - 6 LOW IMP selects between tri-state output (0) or output enabled (1) mode of DACs 5 EN COM enable composite (CVBS) DAC 0: high-impedance, 1: enable 4 EN L enable S-VIDEO Y DAC for luma output 0: high-impedance, 1: enable 3 EN C enable S-VIDEO C DAC for chrom
CS4954 CS4955 Background Color Register 0×08 Address Bit Number Bit Name Default 7 BKG_COLOR Read/Write 6 5 Default Value = 03h 4 3 2 1 0 0 0 1 1 BG 0 Bit Mnemonic 7:0 BG 0 0 0 Function Background color (7:5 = R, 4:2 = G, 1:0 = B) (default is 0000 0011 - blue) GPIO Control Register 0×09 Address Bit Number Bit Name Default 7 GPIO__REG 6 Read/Write 5 Default Value = 00h 4 3 2 1 0 0 0 0 GPR_CNTRL 0 Bit Mnemonic 7:0 GPR CNTRL 0 0 0 0 Function Input(0)/output(1) con
CS4954 CS4955 Sync Register 1 0×0E Address Sync_1 Bit Number Bit Name Default 7 Bit Mnemonic 7:0 PROG HS[7:0] Read/Write 6 5 Default Value = F4h 4 3 2 1 0 1 0 0 2 1 0 0 0 0 PROG HS[7:0] 1 1 1 1 0 Function programmable hsync pixels lsb I²C Address Register Address 0×0F I²C_ADR 7 6 Bit Number Bit Name Default RESERVED Bit Mnemonic 7 - 6:0 I²C Read/Write 5 Default Value = 00h 4 3 I²C ADR 0 0 0 0 0 Function reserved I²C device address (programmable) Subcar
CS4954 CS4955 Hue LSB Adjust Register Address 0×15 Bit Number Bit Name Default 7 HUE_LSB Read/Write 6 5 Default Value = 00h 4 3 2 1 0 0 0 0 0 HUE LSB 0 Bit Mnemonic 7:0 HUE LSB 0 0 0 Function 8 LSBs for hue phase shift Hue MSB Adjust Register Address 0×16 Bit Number Bit Name Default 7 HUE_MSB 6 Read/Write 5 Default Value = 00h 4 3 2 1 RESERVED 0 Bit Mnemonic 7:2 - 1:0 HUE MSB 0 0 0 MSB 0 0 0 0 0 Function reserved 2 MSBs for hue phase shift SCH Sync Phase
CS4954 CS4955 Closed Caption Data Register Address 0×19 0×1A 0×1B 0×1C Bit Mnemonic 7:0 CC_21_1 first closed caption databyte of line 21 7:0 CC_21_2 second closed caption databyte of line 21 7:0 CC_284_1 first closed caption databyte of line 284 7:0 CC_284_2 second closed caption databyte of line 284 CC_21_1 CC_21_2 CC_284_1 CC_284_2 Read/Write Default Value = 00h 00h 00h 00h Function Wide Screen Signaling Register 0 Address Bit Number Bit Name Default 46 0×1E WSS_REG_0 Read/Write De
CS4954 CS4955 Wide Screen Signalling Register 1 0×1F Address Bit Number Bit Name Default WSS_REG_1 Read/Write Default Value = 00h 7 6 5 4 3 2 1 0 WSS_15 WSS_14 WSS_13 WSS_12 WSS_11 WSS_10 WSS_9 WSS_8 0 0 0 0 0 0 0 0 Bit Mnemonic Function 7 WSS_15 PAL: group 2, bit 7, NTSC: bit 16 6 WSS_14 PAL: group 2, bit 6, NTSC: bit 15 5 WSS_13 PAL: group 2, bit 5, NTSC: bit 14 4 WSS_12 PAL: group 2, bit 4, NTSC: bit 13 3 WSS_11 PAL: group 1, bit 3, NTSC: bit 12 2 WSS_10 P
CS4954 CS4955 Filter Register 1 0×23 Address Bit Number Bit Name Default 7 CR_AMP 6 Read/Write 5 Default Value = 80h 4 3 2 1 0 0 0 0 0 V_AMP 1 Bit Mnemonic 7:0 V_AMP 0 0 0 Function V(Cr) amplitude coefficient Filter Register 2 0×24 Address Bit Number Bit Name Default 7 Y_AMP 6 Read/Write 5 Default Value = 80h 4 3 2 1 0 0 0 0 0 Y_AMP 1 Bit Mnemonic 7:0 Y_AMP 0 0 0 Function Luma amplitude coefficient Filter Register 3 0×25 Address Bit Number Bit Name Default 7
CS4954 CS4955 Filter Register 5 0×27 Address Bit Number Bit Name Default 7 B_AMP 6 Read/Write 5 Default Value = 80h 4 3 2 1 0 0 0 0 0 2 1 0 0 0 0 B_AMP 1 Bit Mnemonic 7:0 B_AMP 0 0 0 Function Blue amplitude coefficient Filter Register 6 Address 0×28 Bit Number Bit Name Default 7 Bright_Offsett 6 Read/Write 5 Default Value = 00h 4 3 BRIGHTNESS_OFFSET 0 Bit Mnemonic 7:0 BRGHT_OFFSET 0 0 0 0 Function Brightness adjustment ( range: -128 to +127) Teletext Register
CS4954 CS4955 Teletext Register 2 Address 0×2B Bit Number Bit Name Default 7 TTXOVS 6 Read/Write 5 Default Value = 00h 4 3 2 1 0 0 0 0 0 TTXOVS 0 Bit Mnemonic 7:0 TTXOVS 0 0 0 Function Start of teletext line window in odd field Teletext Register 3 Address 0×2C Bit Number Bit Name Default 7 TTXOVE 6 Read/Write 5 Default Value = 00h 4 3 2 1 0 0 0 0 0 TTXOVE 0 Bit Mnemonic 7:0 TTXOVE 0 0 0 Function End of teletext line window in odd field Teletext Register 4 Ad
CS4954 CS4955 Teletext Register 6 Address 0×2F Bit Number Bit Name Default Bit 7:0 7 TTX_DIS1 Read/Write 6 5 Default Value = 00h 4 3 2 1 0 0 0 0 TTX_LINE_DIS1 0 0 0 0 Mnemonic 0 Function Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all TTX_LINE_DIS1 eight lines are disabled), (MSB is for line 5, LSB is for line 12) Teletext Register 7 Address 0×30 Bit Number Bit Name Default Bit 7:0 TTX_DIS2 Read/Write 7 6 5 0 0 0 Default Value = 00h 4 3
CS4954 CS4955 Interrupt Register 0 Address 0×32 Bit Number Bit Name Default INT_EN 7 Read/Write 6 5 Default Value = 00h 4 3 RESERVED 0 0 0 0 2 1 0 INT_21_EN INT_284_EN INT_V_EN 0 0 0 0 Bit Mnemonic Function 7:3 - 2 INT_21_EN interrupt enable for closed caption line 21 1 INT_284_EN interrupt enable for closed caption line 284 0 INT_V_EN reserved interrupt enable for new video field Interrupt Register 1 Address 0×33 INT_CLR Bit Number Bit Name Default 7 6 Read/Write
CS4954 CS4955 9. BOARD DESIGN AND LAYOUT CONSIDERATIONS The printed circuit layout should be optimized for lowest noise on the CS4954/5 placed as close to the output connectors as possible. All analog supply traces should be as short as possible to minimize inductive ringing. A well designed power distribution network is essential in eliminating digital switching noise. The ground planes must provide a low-impedance return path for the digital circuits.
CS4954 CS4955 This reduces the total power that the CS4954/5 requires, and eliminates the impedance mismatch presented by an unused connector. The analog outputs should not overlay the analog power plane in order to maximize high frequency power supply rejection. 9.5 Analog Output Protection To minimize the possibility of damage to the analog output sections, make sure that all video connectors are well grounded.
CS4954 CS4955 L1 Ferrite Bead Vcc 4.7 μF 15 14 NC 16 0.1 μF 17 VDD XTALIN 36 41 46 VAA VREF 38 XTALOUT PADDR 75 or 300 Ω ∗ RED 39 30 TTXDAT 31 Gpio port 26-19 27 Vcc 1.5 kΩ 28 33 40 75 or 300 Ω ∗ PDAT[7:0] RD BLUE 43 75 or 300 Ω ∗ CVBS 44 Composite Video Connector 75 or 300 Ω ∗ WR 1.5 kΩ 110 Ω 32 I²C Controller GREEN TTXRQ CS4954 CS4955 SDA Y SCL 48 to SCART Connector * Identical load resistors are to be used at the receive 75 or 300 Ω ∗ device.
CS4954 CS4955 10.
CS4954 CS4955 Pin Name V [7:0] CLK PADDR XTAL_IN XTAL_OUT HSYNC/CB VSYNC FIELD/CB(1) RD WR PDAT [7:0] SDA SCL CVBS Y C R G B VREF ISET TTXDAT TTXRQ INT RESET TEST VAA GNDD VDD GNDA Pin Number 8, 7, 6, 5, 4, 3, 2, 1 29 16 15 14 10 Type IN IN IN IN OUT I/O Description Digital video data inputs 27 MHz input clock Address enable line subcarrier crystal input subcarrier crystal output Active low horizontal sync, or composite blank signal 11 9 27 I/O OUT(1) IN Active low vertical sync. Video field ID.
CS4954 CS4955 11. PACKAGE DRAWING 48L TQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L INCHES MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° ∝ * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L MAX 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° MILLIMETERS MIN MAX --1.60 0.05 0.15 0.17 0.27 8.70 9.30 6.90 7.10 8.70 9.30 6.90 7.10 0.40 0.60 0.45 0.75 0.00° 7.00° Controlling dimension is mm.
CS4954 CS4955 12. REVISION HISTORY Revision Date Change F1 July 1999 Initial release F2 April 2004 Corrected List of Figures F3 September 2004 F4 August 2005 F5 F6 DS278F6 July 2006 Added lead free package option (CS4955). Updated ordering information. Added lead-free package for CS4954; deleted CQ packages; updated Revision History and Legal notice.
CS4954 CS4955 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).
