Manual

128-Pin LQFP Pin Assigments
CS4953xx Hardware User’s Manual
DS732UM10 Copyright 2010 Cirrus Logic, Inc 9-16
9.6 128-Pin LQFP Pin Assigments
Figure 9-12 shows the 128-Pin LQFP Pin Layout.
Figure 9-12. 128-Pin LQFP Pin Layout
GPIO2, UART_TXD
GPIO1, UART_RXD
GPIO0, UART_CLK
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
10
15
20
25
30
GPIO6, SCP2_CS
GPIO38, SCP2_CLK
VDD6 GND6
GPIO10, SCP2_MOSI
GPIO8, SCP2_IRQ
GPIO37, SCP1_BSY VDDIO6
GPIO11, SCP2_MISO / SDA
GNDIO6
GPOI9, SCP1_IRQ
GPIO34, SCP1__MISO / SD
A
GPIO33, SCP1_MOSI GPIO35, SCP1_CLK VDD5
VDDIO5
GND5 GNDIO5 SD_CAS SD_RAS
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
125 120 115 110 105
SD_A10, EXT_A10
SD_A11, EXT_A1
1
VDD4
GND4
SD_CS
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D1
0
SD_D11, EXT_D1
1
SD_D12, EXT_D1
2
VDD3
GND3
SD_D13, EXT_D1
3
SD_D14, EXT_D1
4
SD_D15, EXT_D1
5
SD_DQM1
SD_D7, EXT_D7 SD_D6, EXT_D6
VDDIO3
GNDIO3
SD_D5, EXT_D5
SD_DQM0
SD_D4, EXT_D4 SD_D3, EXT_D3 SD_D2, EXT_D2
95
90
85
80
75
70
G
PIO17, DAO1_DATA3 / XMTA
GPIO15, DAO1_DATA1, HS1
DAO1_DATA0, HS0
DAO1_LRCLK
DAI1_LRCLK, DSD5
DAO_MCLK
GPIO20, DAO2_DATA2, EE_CS
DAI1_SCLK, DSD_CLK
VDD1
GND1
DAO1_SCLK
GPIO16, DAO1_DATA2, HS2
GPIO23, DAO2_LRCLK RESET
VDDIO1
GPIO22, DAO2_SCLK
GNDIO1
GPIO18, DAO2_DATA0, HS3 GPIO19, DAO2_DATA1, HS4
VDD2
GND2
G
PIO26, DAO2_DATA3 / XMTB/UART_TX_EN
VDDIO2
GNDIO2
SD_WE
SD_D0, EXT_D0
SD_D1, EXT_D1
40 45 50 55 60
SD_D8, EXT_D8
SD_D9, EXT_D9
SD_A12, EXT_A1
2
SD_BA1, EXT_A14 SD_BA0, EXT_A13
GPIO7, SCP1_CS, IOWAIT
VDDIO8
GNDIO8
EXT_A15 EXT_A16 EXT_A17 EXT_A18 EXT_A19 EXT_CS1 EXT_OE
EXT_WE
GPIO3, DDAC
TEST
DBDA
DBCK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
GPIO42, BDI_REQ , DAI2_LRCLK
DAI1_DATA4, BDI_DATA, DAI2_DATA, DSD4
CS495xx3
128 LQFP
5
35
EXT_CS2
1
65
100