Owner's manual

CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
20 Copyright 2009 Cirrus Logic DS876F3
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
D
ELPHI
Figure 9. Digital Audio Output Port Timing, Master Mode
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
DAO_SCLK
DAO_LRCLK
D
AOn_DATAn
t
daosstlr
t
daosclk
D
AO_SCLK
D
AO_LRCLK
t
daoslrts
t
daosd
v
t
daosclk
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK