User`s manual

9-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7
Pin Assignments
CS485xx Hardware User’s Manual
9.6 Pin Assignments
Table 9-9 shows the names and functions for each pin of the CS48560.
Table 9-9. Pin Assignments of CS48560
LQFP-48
Pin # Function 1
(Default)
Description of Default
Function
Secondary Functions
Description of Secondary Functions Pwr Type
Reset
State
Pullup
at
Reset
1 TEST Test 3.3V (5V tol)
IN
2 RESET Active Low Chip Reset 3.3V (5V tol)
IN
3 DBDA Debug Data 3.3V (5V tol)
BiDi IN Y
4 GNDD1 Core ground 0V
PWR
5 DBCK Debug Clock 3.3V (5V tol)
BiDi IN Y
6 DAI1_LRCLK PCM Audio Input Sample
Rate (Left/Right) Clock
1. DAI1_DATA4
2. DSD5
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
IN Y
7 GNDIO1 I/O ground 0V
PWR
8 DAI1_SCLK PCM Audio Input Bit Clock 1. DSD_CLK 1. DSD Audio Input Clock 3.3V (5V tol)
IN Y
9 GNDD2 Core ground 0V
PWR
10 GPIO16 General Purpose Input/Output 1. DAI1_DATA0
2. DSD0
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
BiDi IN Y
11 GPIO0 General Purpose Input/Output 1. DAI1_DATA1
2. DSD1
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
BiDi IN Y
12 VDDIO1 I/O power supply voltage 3.3V
PWR
13 GPIO1 General Purpose Input/Output 1. DAI1_DATA2
2. DSD2
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
BiDi IN Y
14 GPIO2 General Purpose Input/Output 1. DAI1_DATA3
2. DSD3
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
BiDi IN Y
15 GPIO17 General Purpose Input/Output 1. DAI2_DATA0
2. DSD4
1. Digital Audio Input Data
2. DSD Audio Input Data
3.3V (5V tol)
BiDi IN Y
16 VDDD1 Core power supply voltage 1.8V
PWR
17 GPIO14 General Purpose Input/Output 1. DAI2_LRCLK 1. PCM Audio Input Sample Rate (Left/
Right) Clock
3.3V (5V tol)
BiDi/OD IN Y
18 GPIO15 General Purpose Input/Output 1. DAI2_SCLK PCM Audio Input Bit Clock 3.3V (5V tol)
BiDi IN Y
19 GNDIO2 I/O ground 0V
PWR
20 DAO1_DATA0 Digital Audio Output 0 1. HS0 1. Hardware Strap Mode Select. 3.3V (5V tol)
BiDi IN
21 DAO_LRCLK PCM Audio Sample Rate
Clock
3.3V (5V tol)
BiDi IN Y
22 GNDD3 Core ground 0V
PWR
23 DAO_SCLK PCM Audio Output Bit Clock 3.3V (5V tol)
BiDi IN Y
24 VDDIO2 I/O power supply voltage 3.3V
PWR
25 GPIO18 General Purpose Input/Output 1. DAO_MCLK 1. Audio Master Clock 3.3V (5V tol)
BiDi IN Y
26 GPIO4 General Purpose Input/Output 1. DAO1_DATA2
2. HS2
1. Digital Audio Output
2. Hardware Strap Mode Select
3.3V (5V tol)
BiDi IN Y
27 GPIO3 General Purpose Input/Output 1. DAO1_DATA1
2. HS1
1. Digital Audio Output
2. Hardware Strap Mode Select
3.3V (5V tol)
BiDi IN Y
28 VDDD2 Core power supply voltage 1.8V
PWR
29 GPIO5 General Purpose Input/Output 1. DAO1_DATA3
2. XMTA
1. Digital Audio Output
2. S/PDIF Audio Output A
3.3V (5V tol)
BiDi IN Y
30 GNDIO3 I/O ground 0V
PWR
31 GPIO6 General Purpose Input/Output 1. DAO2_DATA0
2. HS3
1. Digital Audio Output
2. Hardware Strap Mode Select
3.3V (5V tol)
BiDi IN Y
32 GPIO7 General Purpose Input/Output 1. DAO2_DATA1
2. HS4
1. Digital Audio Output
2. Hardware Strap Mode Select
3.3V (5V tol)
BiDi IN Y
33 GNDD4 Core ground 0V
PWR
34 GPIO9 General Purpose Input/Output 1. SCP_MOSI 1. SPI Mode Master Data Output/Slave Data
Input
3.3V (5V tol)
BiDi IN Y
35 GPIO10 General Purpose Input/Output 1. SCP_MISO
2. SCP_SDA
1. SPI Mode Master Data Input/Slave Data
Output
2. I
2
C Mode Master/Slave Data IO
3.3V (5V tol)
BiDi/OD IN Y