User`s manual

DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-12
Serial Control Port Configuration
CS485xx Hardware User’s Manual
Figure 3-10. Sample Waveform for I
2
C Write Functional TIming
Note: The I
2
C slave is always responsible for driving the ACK for the address byte.
Figure 3-11. Sample Waveform for I
2
C Read Functional Timing
Notes: 1.The I
2
C slave is drives the ACK for the address byte.
2.The I
2
C master is responsible for controlling ACK during I
2
C reads. In general, the receiver in an I
2
C transaction is responsible for
providing ACK.
3.SCP_IRQ
remains low until the rising edge of the clock for the last bit of the last byte read from the I
2
C slave.
4.A NACK is sent by the master after the last byte to indicate the end of the read cycle. This must be followed with an I
2
C Stop condition or
I
2
C Repeated-Start condition.
Start
S
CP_CLK
S
CP_SDA Data Byte 3 (MSB)
Stop
7-bit Address
R/W
A
C
K
A
CK
Data Byte 2
A
C
K
Data Byte 1
A
C
K
Data Byte 0 (LSB)
ACK
M S M S M S M S M S M
Start
SCP_CLK
SCP_SDA
Data Byte 3 (MSB)
Stop
7-bit Address
R/W
ACK
AC
K
Data Byte 2
ACK
Data Byte 1
AC
K
Data Byte 0 (LSB)
SCP_IRQ
N
A
CK
M S S M S M S M S M M
M = Master Drives SDA
S = Slave Drives SDA