CS485xx 32-bit Audio DSP Family CS485xx H ardwa re Us er ’s Manual Copyright 2009 Cirrus Logic http://www.cirrus.
CS485xx Hardware User’s Manual Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
Contents CS485xx Hardware User’s Manual Contents Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents CS485xx Hardware User’s Manual 3.2.2.1 I2C Bus Dynamics..........................................................................................3-4 3.2.2.2 I2C Messaging ...............................................................................................3-7 3.2.2.3 Performing a Serial I2C Write ........................................................................3-7 3.2.2.4 Performing a Serial I2C Read ........................................................................3-9 3.
Figures CS485xx Hardware User’s Manual 8.2.1.2 Ground.........................................................................................................8-11 8.2.1.3 Decoupling...................................................................................................8-11 8.2.2 PLL Filter ......................................................................................................................8-11 8.2.2.1 Analog Power Conditioning ....................................................
Figures CS485xx Hardware User’s Manual Figure 3-18. Sample Waveform for SPI Read Functional Timing ..............................................................3-21 Figure 4-1. 10-Channel DAI Port Block Diagram .........................................................................................4-3 Figure 4-2. 8-Channel DAI Port Block Diagram ...........................................................................................4-3 Figure 4-3. 6-Channel DAI Port Block Diagram .....................
Tables CS485xx Hardware User’s Manual Tables Table 1-1. List of Available Firmware Modules and Associated Application Note. .......................................1-4 Table 1-2. Device and Firmware Selection Guide ........................................................................................1-7 Table 2-1. Operation Modes .........................................................................................................................2-2 Table 2-2. SLAVE_BOOT message for CS485xx ...........
Tables CS485xx Hardware User’s Manual Table 8-5. PLL Filter Pins ...........................................................................................................................8-12 Table 8-6. Reference PLL Component Values ...........................................................................................8-12 Table 8-7. DSP Core Clock Pins ................................................................................................................8-13 Table 8-8. Reset Pin ...........
Overview CS485xx Hardware User’s Manual Chapter 1 Introduction 1.1 Overview The CS485xx is a programmable audio DSP that combines a programmable, 32-bit fixed-point, generalpurpose DSP with dedicated audio peripherals. Its “audio-centric” interfaces facilitate the coding of highprecision audio applications and provide a seamless connection to external audio peripheral ICs.
Overview CS485xx Hardware User’s Manual Figure 1-1 illustrates the functional block diagram for CS48560.
Overview CS485xx Hardware User’s Manual Figure 1-2 illustrates the functional block diagram for CS48540.
Overview CS485xx Hardware User’s Manual Figure 1-3 illustrates the functional block diagram for CS48520.
Code Overlays CS485xx Hardware User’s Manual This chip, teamed with Cirrus digital interface products and mixed-signal data converters, enables the design of next-generation digital entertainment products. Licenses are required for all of the 3rd party audio processing algorithms listed in "Code Overlays". Please contact your local Cirrus Logic Sales representative for more information. 1.
Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual Table 1-1 lists the firmware available based on device selection. Please refer AN298, CS485xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available. Table 1-1.
Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual buffers which are 32 bits wide. The O/S can dedicate DMA channels to fill the DAO data buffers from memory. DAO control is handled through the peripheral bus. 1.3.4 Digital Audio Input (DAI) Controller The CS485xx Digital Audio Input (DAI) controller can operate with a single clock domain or in a dual-clockdomain mode.
Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual 1.3.8 Serial Flash Controller The CS485xx boot ROM supports a protocol that allows autoboot from a serial Flash or EEPROM device. Boot modes are supported for 13-bit addressing, 16-bit addressing, and 20-bit addressing. A dedicated FLASH/EEPROM (EE_CS) chip select pin allows Flash devices to be connected without additional chip select logic. 1.3.9 DMA Controller The DMA controller contains 8 channels.
Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual 1.3.13 Programmable Interrupt Controller The Programmable Interrupt Controller (PIC) forces all incoming interrupts to be synchronized to the global clock, HCLK. The PIC provides up to 16 interrupts to the DSP Core. The interrupts are prioritized with interrupt 0 as the highest priority and interrupt 15 as the lowest priority. Each interrupt has a corresponding interrupt address that is also supplied to the DSP core.
Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual DS734UM7 Copyright 2009 Cirrus Logic, Inc.
Introduction CS485xxr Hardware User’s Manual Chapter 2 Operational Modes 2.1 Introduction The CS485xx has several operational modes that can be used to conform to many system configurations. The operational modes for the CS485xx specify both the communication mode and boot mode. This chapter discusses the selection of operational modes, booting procedures and process of performing a soft reset. The CS485xx can be either a slave device or a master device for the boot procedure.
Operational Mode Selection CS485xxr Hardware User’s Manual 2.2 Operational Mode Selection The operational mode for the CS485xx is selected by the values of the HS[4:0] pins on the rising edge of RESET. This value determines the communication mode used until the part is reset again. This value also determines the method for loading application code. The table below shows the different operational modes and the HS[4:0] values for each mode. Table 2-1.
Slave Boot Procedures CS485xxr Hardware User’s Manual Pseudocode and flowcharts will be used to describe each of these boot procedures in detail. The flow charts use the following messages: • Write_* – Write to CS485xx • Read_* – Read from CS485xx Please note that * above can be replaced by SPI™ or I2C® depending on the mode of host communication. For each case, the general download algorithm is the same.
Slave Boot Procedures CS485xxr Hardware User’s Manual START RESET (LOW) SET HS[3:0] PINS FOR OPERATIONAL MODE RESET (HIGH) WAIT 50 μS WRITE_* (SLAVE_BOOT) READ_* (MSG) MSG ==BOOT_START N EXIT(ERROR) Y SEND .ULD FILE READ_* (MSG) MSG== BOOT_SUCCESS N EXIT (ERROR) Y Y MORE .ULD FILES? N WRITE_* (SOFT_RESET) READ_* (MSG) MSG ==APP_START N EXIT (ERROR) Y SEND HARDWARE CONFIGURATIONS SEND FIRMWARE CONFIGURATIONS * is replaced with SPI, I2C, etc.
Slave Boot Procedures CS485xxr Hardware User’s Manual 2.3.2.1 Slave Boot Procedure 1. Toggle RESET. A download sequence is started when the host holds the RESET pin low for the required time. The mode pins (HS[4:0]) must be in the appropriate state to set the host communication mode before and immediately after the rising edge of RESET. Pull-up and pull-down resistors are typically used to set the default state of the HS[4:0] pins. 2. Send the SLAVE_BOOT message.
Slave Boot Procedures CS485xxr Hardware User’s Manual 2.3.3 Boot Messages The Slave Boot procedure uses a number of messages to configure and synchronize the boot process. Please use the messages listed below when implementing the boot process as a part of the system host controller firmware. 2.3.3.1 Slave Boot Table 2-2. SLAVE_BOOT message for CS485xx MNEMONIC VALUE SLAVE_BOOT 0x80000000 The SLAVE_BOOT message is used when the system host controller will send each.uld file directly to the CS485xx.
Master Boot Procedure CS485xxr Hardware User’s Manual Table 2-5 is a quick reference showing the different boot commands understood by the CS485xx, in mnemonic and actual hex value, used in CS485xx boot sequences. Table 2-5. Boot Command Messages for CS485xx MNEMONIC VALUE DETAILED TABLE SLAVE_BOOT 0x80000000 Table 2-2 SOFT_RESET 0x40000000 Table 2-3 2.4 Master Boot Procedure A master boot sequence is initiated immediately after the rising edge of RESET.
Softboot CS485xxr Hardware User’s Manual 2.5 Softboot The O/S application code for the CS485xx allows users to swap out one or more overlays during run time, without the need for re-download of the entire overlay stack. This is helpful for reducing the time required for switching between different types of incoming audio data streams.
Softboot CS485xxr Hardware User’s Manual START WRITE_* (SOFTBOOT) N IRQ == LOW? Y READ_* (MSG) N N TIMEOUT? Y EXIT(ERROR) MSG == SOFTBOOT_ACK? Y LOAD OVERLAYS DONE Figure 2-4. Soft Boot Sequence Flowchart 2.5.2.1 Softboot Steps 1. Send the SOFTBOOT message. The host sends the SOFTBOOT message to the CS485xx to begin overlay swap. 2. Wait for IRQ low. The host then waits for SCP_IRQ to go low. If the TIMEOUT period has been reached, the host should exit. If the IRQ pin is LOW, proceed to step 3. 3.
Softboot CS485xxr Hardware User’s Manual START WRITE_* (SOFTBOOT) N IRQ == LOW? N TIMEOUT? Y Y READ_* (MSG) N EXIT(ERROR) MSG == SOFTBOOT_ACK? Y WRITE_* (SLAVE_BOOT) READ_* (MSG) MSG ==BOOT_START N EXIT(ERROR) Y SEND .ULD FILE READ_* (MSG) MSG== BOOT_SUCCESS N EXIT(ERROR) Y Y MORE .ULD FILES? N WRITE_* (SOFT_RESET) READ_* (MSG) MSG ==APP_START N EXIT(ERROR) Y SEND HARDWARE CONFIGURATIONS SEND FIRMWARE CONFIGURATIONS * is replaced with SPI, I2C, etc.
Softboot CS485xxr Hardware User’s Manual 3. Read the SOFTBOOT_ACK message. If the message is the SOFTBOOT_ACK message (0x00000005), then the host should proceed to step 4. If the message is not the SOFTBOOT_ACK message, the host should return to step 2. 4. Send the SLAVE_BOOT message. The host sends the SLAVE_BOOT message to the CS485xx using the format specified (I2C or SPI) by the HS[4:0] pins at reset. 5. Wait for IRQ low. The host then waits for SCP_IRQ to go low. 6. Read the BOOT_START message.
Low Power Mode CS485xxr Hardware User’s Manual 2.6 Low Power Mode The CS485xx has a low power mode to enable power savings when not in use. Low power mode is entered during the softboot procedure. 2.6.1 Low Power Mode Messaging One message is relevant to the low power mode procedure for the CS48xxxx. This message is SOFTBOOT_LP. The host must read any ACK and prior messages before low power mode may commence. Mnemonic Value SOFTBOOT_LP 0x81000009 0x00000011 2.6.
Low Power Mode CS485xxr Hardware User’s Manual Start SET DSP_RESET (LOW) SET DSP_RESET (HIGH) WRITE_* (SLAVE_BOOT) READ_* (MSG) MSG== BOOT_START Y N EXIT (ERROR) Y SEND .ULD FILE Send .uld from Table 2-8 READ_* (MSG) MSG== BOOT_SUCCESS N EXIT (ERROR) Y WRITE_* (SOFT_RESET) READ_* (MSG) MSG== APP_START N EXIT (ERROR) Y SEND HARDWARE CONFIGURATIONS SEND SOFTWARE CONFIGURATIONS WRITE_* (KICKSTART) DONE Figure 2-6.
Low Power Mode CS485xxr Hardware User’s Manual 0x Table 2-8. wakeup_uld Options and Values .uld Options Values WAKEUP_P2.ULD 0x08004409 0x00000002 0x00000000 0xb485aa01 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e9b WAKEUP_P4.ULD0x 0x08004409 0x00000002 0x00000001 0xb485aa01 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e9a WAKEUP_P6.ULD 0x08004409 0x00000002 0x00000002 0xb485aa01 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e99 WAKEUP_P8.
Introduction CS485xx Hardware User’s Manual Chapter 3 Serial Control Port 3.1 Introduction The CS485xx uses the Serial Control Port (SCP) to communicate with external devices such as host microprocessors using either I2C or SPI serial communication formats. The port can be configured as either a master or slave. The CS485xx DSP serial port communicates using the SCP_CLK, SCP_MOSI, SCP_MISO (SPI serial master and slave modes), and SCP_SDA (for I2C serial master and slave modes) pins.
Serial Control Port Configuration CS485xx Hardware User’s Manual 3.2.1 I2C Port The CS485xx I2C bus has been developed for 8-bit digital control applications, such as those requiring microcontrollers. The I2C bus interface is a bidirectional serial port that uses 2 lines (data and clock) for data transmission and reception with software-addressable external devices.
Serial Control Port Configuration CS485xx Hardware User’s Manual 3.2.2 I2C System Bus Description Devices can be considered masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device addressed by the initiator is considered a slave. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it.
Serial Control Port Configuration CS485xx Hardware User’s Manual Table 3-1. Serial Control Port 1 I2C Signals Pin Name Pin Description LQFP-48 Pin # Pin Type SCP_CLK I2C Control Port Bit Clock. In master mode, this pin serves as the serial control clock output (open drain in I2C mode / output in SPI mode). In serial slave mode, this pin serves as the serial control clock input. In I2C slave mode the clock can be pulled low by the port to stall the master.
Serial Control Port Configuration CS485xx Hardware User’s Manual The number of bytes that can be transmitted per transfer is unrestricted. Data is transferred with the mostsignificant bit (MSB) first. The first byte is an address byte that is always sent by the master after a Start or repeated Start condition. This byte must be a 7-bit I2C slave address + R/W bit. The 7-bit I2C address for the CS485xx is 1000000b (0x80).
Serial Control Port Configuration CS485xx Hardware User’s Manual Start SCP_CLK SCP_SDA A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Data Byte ACK Write M S M S Read M S S M Data Byte NACK Start SCP_CLK SCP_SDA A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Write M S M S Read M S S M M = Master Drives SDA S = Slave Drives SDA Figure 3-5.
Serial Control Port Configuration CS485xx Hardware User’s Manual Start SCP_CLK SCP_SDA Data Byte ACK A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W Write M S M S Read S M M S ACK Start SCP_CLK SCP_SDA Data Byte NACK A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Write M S M S Read S M M S M = Master Drives SDA S = Slave Drives SDA Figure 3-7. Repeated Start Condition with ACK and NACK 3.2.2.
Serial Control Port Configuration CS485xx Hardware User’s Manual SEND I2C START: DRIVE SCP_SDA LOW WHILE SCP_CLK IS HIGH WRITE ADDRESS BYTE 0x80 N EXIT (ERROR) SCP_SDA == ACK? Y SEND DATABYTE N EXIT (ERROR) SCP_SDA == ACK? Y N 4 BYTES SENT? Y N Y MORE DATA? SCP_BSY (LOW)? N Y I2C STOP: DRIVE SCP_SDA HIGH WHILE SCP_CLK IS HIGH Figure 3-8. I2C Write Flow Diagram 3.2.2.3.1 I2C Write Protocol Procedure 1.
Serial Control Port Configuration CS485xx Hardware User’s Manual after each byte, the master must provide an acknowledge clock pulse on SCP_CLK and release the data line, SCP_SDA. 6. If the master has no more data words to write to the CS485xx, then proceed to step 8. If the master has more data words to write to the CS485xx, then proceed to step 7. 7. The master should poll the SCP_BSY signal until it goes high.
Serial Control Port Configuration CS485xx Hardware User’s Manual START N SCP_IRQ (LOW)? Y SEND I2C START: DRIVE SCP_SDA LOW WHILE SCP_CLK IS HIGH WRITE ADDRESS BYTE 0x81 N EXIT (ERROR) SCP_SDA == ACK? Y READ DATA BYTE SEND ACK BYTES READ = 4? N Y SCP_IRQ LOW? Y N SEND NACK SEND I2C STOP: DRIVE SCP_SDA HIGH WHILE SCP_CLK IS HIGH Figure 3-9. I2C Read Flow Diagram DS734UM7 Copyright 2009 Cirrus Logic, Inc.
Serial Control Port Configuration CS485xx Hardware User’s Manual 3.2.2.4.1 I2C Read Protocol Procedure 1. An I2C read transaction is initiated by CS485xx driving SCP_IRQ low, signaling that it has data to be read. 2. The master responds by sending an I2C Start condition which is SCP_SDA going low while SCP_CLK is held high. 3. This is followed by a 7-bit address and the read/write bit set high for a read. So, the master should send 0x81.
DS734UM7 Start Stop M S M Data Byte 1 S M Data Byte 0 (LSB) AC K S Data Byte 2 AC K M Data Byte 3 (MSB) AC K 7-bit Address AC K SCP_SDA R /W AC K SCP_CLK S M S M Figure 3-10. Sample Waveform for I2C Write Functional TIming Note: The I2C slave is always responsible for driving the ACK for the address byte. Stop Data Byte 0 (LSB) K Data Byte 1 NA C Data Byte 2 AC K Data Byte 3 (MSB) AC K 7-bit Address AC K SCP_SDA /W AC K SCP_CLK R Copyright 2009 Cirrus Logic, Inc.
SPI Port CS485xx Hardware User’s Manual If there are more data words to read, IRQ will fall at the rising edge of CLK for the NACK. Otherwise, IRQ remains high until an I2C Stop condition or an I2C Repeated-Start condition occurs. 3.3 SPI Port The CS485xx Serial Peripheral Interface (SPI) bus has been developed for 8-bit digital control applications, such as those requiring microcontrollers.
SPI Port CS485xx Hardware User’s Manual Table 3-2. Serial Control Port SPI Signals Pin Name Pin Description LQFP-48 Pin # Pin Type SCP_CS SPI Chip Select, Active Low In serial SPI slave mode, this pin is used as the active-low chip-select input signal. In SPI serial master mode, if this pin is driven low by another master device on the bus, it will cause a mode fault to occur. 38 Input SCP_CLK SPI Control Port Bit Clock In master mode, this pin serves as the serial control clock output.
SPI Port CS485xx Hardware User’s Manual Both modes of the CS485xx serial port are shown in Figure 3-13. 3.3V 3.3k System Microcontroller 3.3k CS485xx GPIO RESET GPIO SCK MOSI MISO SCP_CS SCP_CLK SCP_MOSI SCP_MISO SCP_IRQ SCP_BSY GPIO GPIO SLAVE ONLY CS485xx SPI EEPROM MOSI MISO CS CLK SCP_MOSI SCP_MISO SCP_CS SCP_CLK MASTER ONLY Figure 3-13. Block Diagram of SPI System Bus 3.3.1.1 SPI Bus Dynamics A SPI transaction begins by the master driving the slave chip select SCP_CS low.
SPI Port CS485xx Hardware User’s Manual SCP_CS SCP_CLK SCP_MOSI 7-bit SPI Address R/W 7-bit SPI Address R/W Data Byte SCP_CS SCP_CLK SCP_MOSI SCP_MISO Data Byte SCP_CS SCP_CLK SCP_MOSI 7-bit SPI Address R/W 7-bit SPI Address R/W Data Byte SCP_CS SCP_CLK SCP_MOSI SCP_MISO Data Byte SCP_CS SCP_CLK SCP_MOSI 7-bit SPI Address R/W 7-bit SPI Address R/W Data Byte SCP_CS SCP_CLK SCP_MOSI SCP_MISO Data Byte Figure 3-14. SPI Address and Data Bytes 3.3.1.1.
SPI Port CS485xx Hardware User’s Manual 3.3.1.2 SPI Messaging Messaging to the CS485xx using the SPI bus requires usage of all the information provided in the SPI Bus SCP_CS SCP_CLK SCP_MOSI 7-bit SPI Address R/W 7-bit SPI Address R/W Data Byte SCP_CS SCP_CLK SCP_MOSI SCP_MISO Data Byte Description and Bus Dynamics above. For control and application image downloading, SPI transactions to the CS485xx will involve 4-byte words.
SPI Port CS485xx Hardware User’s Manual SPI START: SCP_CS (LOW) WRITE ADDRESS BYTE 0x80 WRITE 4 DATA BYTES Y MORE DATA? SCP_BSY (LOW)? N N Y SPI STOP: SCP_CS (HIGH) Figure 3-15. SPI Write Flow Diagram 3.3.1.3.1 SPI Write Protocol Procedure 1. A SPI transfer is initiated when the chip select SCP_CS is driven low. SCP_CS driven low indicates that CS485xx is in SPI slave mode. 2. This is followed by a 7-bit address and the read/write bit set low for a write. So, the master should send 0x80.
SPI Port CS485xx Hardware User’s Manual When performing a SPI read, the same protocol is used whether reading a single byte or multiple bytes. From a hardware perspective, it makes no difference whether communication is a single byte or multiple bytes of any message length, so long as the correct hardware protocol is followed. The example shown in this section can be generalized to fit any SPI read situation.
SPI Port CS485xx Hardware User’s Manual 5. If SCP_IRQ is still low after 4 bytes, then proceed to step 4 and read another 4 bytes out of the CS485xx slave. 6. If SCP_IRQ is high, the SCP_CS line of CS485xx should be driven high to end the read transaction. DS734UM7 Copyright 2009 Cirrus Logic, Inc.
DS734UM7 SCP_CS SCP_CLK /W 7-bit Address R SCP_MOSI Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) Figure 3-17. Sample Waveform for SPI Write Functional Timing S C P _ M IS O 7 - b it A d d r e s s /W S C P _ M O S I R Copyright 2009 Cirrus Logic, Inc. S C P _ C S S C P _ C L K D a ta B y te 3 (M S B ) D a ta B y te 2 D a ta B y te 1 D a ta B y te 0 (L S B ) S C P _ IR Q Figure 3-18. Sample Waveform for SPI Read Functional Timing Notes: 1.
SPI Port CS485xx Hardware User’s Manual 3.3.1.4.2 SCP_IRQ Behavior The SCP_IRQ signal is not part of the SPI protocol, but is provided so that the slave can signal that it has data to be read. A high-to-low transition on SCP_IRQ indicates to the master that the slave has data to be read. When a master detects a high-to-low transition on SCP_IRQ, it should send a Start condition and begin reading data from the slave.
Introduction CS485xx Hardware User’s Manual Chapter 4 Digital Audio Input Interface 4.1 Introduction CS485xx supports a wide variety of audio data formats through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. This data sheet presents most of the modes available with the CS485xx hardware. However, not all of the modes are available with any particular piece of application code.
Digital Audio Input Port Description CS485xx Hardware User’s Manual 4.2.1 DAI Pin Description Table 4-1 shows the mnemonic and pin description of the pins associated with the DAI port on CS485xx. Table 4-1. Digital Audio Input Port Pin Name Pin Description LQFP-48 Pin # Pin Type DAI1_LRCLK or DAI1_DATA5 Sample Rate Clock 1 PCM Audio Input Sample Rate (LeftRight) Clock DAI1_LRCLK is the sample rate input clock for the serial PCM audio data on DAI_DATA[3:0] when in dual-clock domain mode.
Digital Audio Input Port Description CS485xx Hardware User’s Manual 4.2.2 Supported DAI Functional Blocks The CS485xx DAI has many functional blocks for realizing various audio system configurations. The use of these functions is dependent on the firmware currently available on the CS485xx. 4.2.2.1 Dual Clock Domain - 10 Channel Input Figure 4-1 shows the functional block diagram of the features currently supported with the CS48560 DAI.
DAI1_DATA0 DAI_LRCLK1 DAI_SCLK1 DAI2_DATA0 DAI_LRCLK2 DAI_SCLK2 DAI1_DATA0 DAI2_DATA0 DMA to Peripheral Bus Digital Audio Input Port Description CS485xx Hardware User’s Manual Figure 4-3. 6-Channel DAI Port Block Diagram Currently supported are 4 lines of linear PCM input (DAI1_DATA3:0) on the first clock domain and 1 additional line of linear PCM (DAI2_DATA0) on the second clock domain, which will support up to 10 channels of PCM.
Digital Audio Input Port Description CS485xx Hardware User’s Manual DAI1_DATA0 DAI1_DATA0 DAI1_DATA1 DAI1_DATA2 DAI1_DATA2 DAI1_DATA3 DAI1_DATA3 DMA to Peripheral Bus DAI1_DATA1 DAI1_DATA4 DAI1_DATA4 DAI1_DATA5 DAI_LRCLK2 DAI_SCLK2 DAI1_DATA5 Figure 4-4. 12-Channel DAI Port Block Diagram 4.2.3 Digital Audio Formats The DAI data input pins are fully configurable including support for I2S and left-justified formats. DAI clock and data pins support only slave operation.
DAI Hardware Configuration CS485xx Hardware User’s Manual DAIn_LRCLK Left Channel Right Channel DAIn_SCLK DAI_DATA +5 +4 +3 +2 +1 LSB MSB-1 -2 -3 -4 -5 MSB-1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 4-5. I2S format (Rising Edge Valid SCLK) 4.2.3.2 Left-Justified Format Figure 4-6 illustrates the left-justified format with a rising-edge DAIn_SCLK. Data is presented mostsignificant bit first on the first DAIn_SCLK after a DAIn_LRCLK transition and is valid on the rising edge of DAIn_SCLK.
DAI Hardware Configuration CS485xx Hardware User’s Manual D - DAI Mode (Unsupported) E - DAI2_DATA Clock Source F - DAI1_DATA Clock Source G - Chip Version H - Chip Version Table 4-2, Table 4-3, Table 4-4, Table 4-5, Table 4-6, Table 4-7, and Table 4-7show the different values for each parameter as well as the hex message that needs to be sent to configure the port. When creating the hardware configuration message, only one hex message should be sent per parameter. . Table 4-2.
DAI Hardware Configuration CS485xx Hardware User’s Manual Table 4-3. Input SCLK Polarity Configuration (Input Parameter B) B Value 0 (default) 1 SCLK Polarity (DAI_SCLK1 & DAI_SCLK2) Hex Message Data Clocked in on SCLK Rising Edge 0x81800010 0xFFDFFFFF 0x81800011 0xFFDFFFFF 0x81800012 0xFFDFFFFF 0x81800013 0xFFDFFFFF 0x81800014 0xFFDFFFFF Data Clocked in on SCLK Falling Edge 0x81400010 0x00200000 0x81400011 0x00200000 0x81400012 0x00200000 0x81400013 0x00200000 0x81400014 0x00200000 . Table 4-4.
DAI Hardware Configuration CS485xx Hardware User’s Manual Table 4-5. DAI2_DATA Clock Source (Input Parameter E) E Value DAI2_DATA Clock Source HEX Message 0 DAI1_LRCLK/DAI1_SCLK 0x81800015 0xCFFFFFFF DAI2_LRCLK/DAI2_SCLK 0x81400015 0x10000000 0x81800015 0xDFFFFFFF 1 (default) Table 4-6.
DAI Hardware Configuration CS485xx Hardware User’s Manual a. TDM (Time Division Multiplex) is only available on the CS48560 product. b. Accepts a maximum of 12 channlels of input. §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc.
Digital Audio Input Port Description CS485xx Hardware User’s Manual Chapter 5 Direct Stream Data (DSD) Input Interface CS48560 is capable of accepting DSD audio data directly. DSD data differs from PCM in that audio is provided as a contiguous stream of 1’s and 0’s on a single line. There is no framing clock (LRCLK), and there is only one channel per line. The CS48560 supports internal conversion of DSD data to PCM which can then be processed by the DSP.
Digital Audio Input Port Description CS485xx Hardware User’s Manual DSD0 DSD_DATA0 DSD1 DMA to Peripheral Bus DSD_DATA1 DSD2 DSD_DATA2 DSD3 DSD_CLK DSD_DATA3 DSD4 DSD_DATA4 DSD5 DSD_DATA5 Figure 5-1. DSD Port Block Diagram on CS48560 §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc.
Introduction CS485xx Hardware User’s Manual Chapter 6 Digital Audio Output Interface 6.1 Introduction The CS485xx Digital Audio Output port can provide up to 12 channels of PCM data (up to 32-bit resolution). The Digital Audio Output port is implemented with a modified 3-wire Inter-IC Sound (I2S) interface along with an oversampling master clock (MCLK).
Digital Audio Output Port Description CS485xx Hardware User’s Manual DAO_MCLK is the master clock and is firmware configurable to be either an input (slave) or an output (master). If MCLK is to be used as an output, the internal PLL must be used. As an output MCLK can be configured to provide a 128Fs, 256Fs, or 512Fs clock, where Fs is the output sample rate. • DAO_SCLK is the bit clock used to clock data out on DAOn_DATA[n].
Digital Audio Output Port Description CS485xx Hardware User’s Manual . DAO1_DATA0 Peripheral Bus to DMA DAO1_DATA1 DAO1_DATA2 SPDIF ENCODER XMTA DAO2_DATA0 Clock Manager DAO_MCLK DAO_SCLK DAO_LRCLK Figure 6-2. CS48540 DAO Block Diagram Peripheral Bus to DMA . DAO1_DATA0 SPDIF ENCODER XMTA DAO2_DATA0 Clock Manager DAO_MCLK DAO_SCLK DAO_LRCLK Figure 6-3. CS48520 DAO Block Diagram 6-3 Copyright 2009 Cirrus Logic, Inc.
Digital Audio Output Port Description CS485xx Hardware User’s Manual 6.2.2 Supported DAO Functional Blocks As mentioned in Section 6.1, DAO_DATA3 on CS48560 is unique in that it is designed to serve as either an output for I2S or left-justified PCM data or as a S/PDIF transmitter (XMTA). On the CS48540 and CS48520 it is only a s S/PDIF transmitter (XMTA).
Digital Audio Output Port Description CS485xx Hardware User’s Manual 6.2.3.3 One-line Data Mode Format (Multichannel) The CS485xx is capable of multiplexing all digital audio outputs on one line, as illustrated in Figure 6-6. This mode is available only through special request. Please contact your local Cirrus representative for further details.
Digital Audio Output Port Description CS485xx Hardware User’s Manual Table 6-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B) B Value 0a DAO1 & DAO2 Clocking Relationship Hex Message DAO2 dependent on DAO1 clocks 0x8140001B 0x00002000 a. This command is required because the DAO2 clocks are not bonded out. Please refer to Table 6-4, Table 6-5, and Table 6-6 for examples of the clocking directions for the settings contained in Table 6-2.
Digital Audio Output Port Description CS485xx Hardware User’s Manual Table 6-4.
Digital Audio Output Port Description CS485xx Hardware User’s Manual Table 6-5 shows values and messages for the data format configuration parameters. Table 6-5.
Digital Audio Output Port Description CS485xx Hardware User’s Manual Table 6-6 shows values and messages for the DAO_LRCLK polarity configuration parameter. Table 6-6.
Digital Audio Output Port Description CS485xx Hardware User’s Manual The DAO_DATA3/XMTA S/PDIF output pin on the CS48540 and CS48520 can be configured as: • S/PDIF Transmitter - Sent configuration from Table 6-10 A soft reset is required when switching between any of the above modes. Table 6-9. S/PDIF Transmitter Pins Pin Name Pin Description LQFP-48 Pin # Pin Type DAO_DATA3/XMTA S/PDIF Audio Output A 29 Output Table 6-10.
System Clocking Controls CS485xx Hardware User’s Manual Chapter 7 Crystal Oscillator and System Clocking 7.1 System Clocking Controls The CS485xx incorporates one programmable phase locked loop (PLL) clock synthesizer. The PLL take an input reference clock and produces all the clocks required to run the DSP and peripherals. The input reference clock may come from an external 24.576 MHz oscillator connected to the XTI pin. In this case the XTO pin should be left disconnected.
Configuring the Crystal Oscillator CS485xx Hardware User’s Manual XTAL_OUT To System XTO 1 Meg X1 XTI C1 C1 CS485xx Figure 7-1. Crystal Oscillator Schematic 7.2 Configuring the Crystal Oscillator After code download or soft reset, and before kickstarting the application, the host has the option of changing the default hardware configuration. (Please see AN298, “CS485xx Firmware User’s Manual” for more information on kickstarting).
Introduction CS485xx Hardware User’s Manual Chapter 8 General Purpose Input/Output Pins 8.1 Introduction The CS485xx has up to 19 GPIO pins available for system control functions. In order to fit the most functionality possible into a small package, all of the GPIOs are multiplexed with other audio and control ports on the CS485xx. This means that the number of GPIOs available to a given system depends on how many of the pins are being used for audio functionality.
Watchdog Timer Description CS485xx Hardware User’s Manual 8.3 Watchdog Timer Description As mentioned earlier in the overview of the CS485xx, there is an integrated Watchdog Timer that acts as a “health” monitor for the DSP. The Watchdog Timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure.
Typical Connection Diagrams CS485xx Hardware User’s Manual Chapter 8 System Integration 9.1 Typical Connection Diagrams Figure 9-1 is a typical connection diagram for the CS485xx in SPI slave mode with 10 channels of digital audio input and all audio clocks synchronous to S/PDIF RX. Figure 9-2 is a typical connection diagram for the CS485xx in I2C slave mode with 10 channels of digital audio input, dual-clock domain, output audio clocks synchronous to HDMI Rx.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-2 Typical Connection Diagrams CS485xx Hardware User’s Manual Figure 9-1.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-3 Figure 9-2.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-4 Figure 9-3.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-5 Figure 9-4.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-6 Figure 9-5.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-7 Typical Connection Diagrams CS485xx Hardware User’s Manual Figure 9-6.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-8 Figure 9-7.
DS734UM7 Copyright 2009 Cirrus Logic, Inc. Typical Connection Diagrams CS485xx Hardware User’s Manual 9-9 Figure 9-8. SPI Master, 10 Channels of Digital Audio Input, All Audio Clocks Synchronous to S/PDIF Rx.
Pin Description CS485xx Hardware User’s Manual 9.2 Pin Description 9.2.1 Power and Ground The following sections describe the CS485xx power and ground pins. Decoupling and conditioning of the power supplies is also discussed. Following the recommendations for decoupling and power conditioning will help to ensure reliable performance. 9.2.1.1 Power The CS485xx Family of DSPs take two supply voltages — the core supply voltage (VDD) and the I/O supply voltage (VDDIO).
Pin Description CS485xx Hardware User’s Manual 9.2.1.2 Ground For two-layer circuit boards, care should be taken to have sufficient grounding between the DSP and parts in which it will be interfacing (DACs, ADCs, S/PDIF Receivers, microcontrollers, and especially external memory). Insufficient grounding can degrade noise margins between devices resulting in data integrity problems. Table 9-3.
Clocking CS485xx Hardware User’s Manual 9.2.3 PLL The internal phase locked loop (PLL) of the CS485xx requires an external current reference resistor. The resistor is used to calibrate the PLL and must meet the tolerances specified below. The layout topology is shownTable 9-9. Care should be taken when laying out the current sense circuitry to minimize trace lengths between the DSP and resistor, and to keep high-frequency signals away from the resistor.
Control CS485xx Hardware User’s Manual 9.4.1 Operational Mode The control interface protocol used is determined by the state of the Hardware Strap pins, HS[4:0] which are sampled at the rising edge of RESET. The HS[4:0] pins should be pulled to VDD or GND using 10 kΩ resistors according to the specific control mode desired as shown in Table 2-1 on page 2- 2. The following sections describe the pins used to select the different control modes.
48-Pin LQFP Pin Assigments CS485xx Hardware User’s Manual 9.5 48-Pin LQFP Pin Assigments GPIO4, DAO1_ DATA2, HS2 GPIO18, DAO_MCLK 26 25 GNDIO3 30 GPIO3, DAO1_ DATA1, HS1 GPIO6, DAO2 _DATA0, HS3 31 27 GPIO7, DAO2_D ATA1, HS4 32 VDD2 GND4 33 28 GPIO9, SCP_MOSI 34 GPIO5, DAO1_DATA3, X MTA GPIO10, SCP__MISO / SDA 35 29 GPIO11, SCP_CLK 36 Figure 9-10 shows the 48-Pin LQFP Pin Layout of the CS48560.
48-Pin LQFP Pin Assigments CS485xx Hardware User’s Manual GPIO18, DAO_MCLK GPIO5, XMTA 29 25 GNDIO3 30 GPIO4, DAO1_ DATA2, HS2 GPIO6, DAO2_DATA0, HS3 31 26 GPIO7, HS4 32 GPIO3, DAO1_ DATA1, HS1 GND4 33 27 GPIO9, SCP_MOSI 34 VDD2 GPIO10, SCP__MISO / SDA 35 28 GPIO11, SCP_CLK 36 Figure 9-11 shows the 48-Pin LQFP Pin Layout of the CS48540.
48-Pin LQFP Pin Assigments CS485xx Hardware User’s Manual GPIO4, HS2 GPIO18, DAO_MCLK 26 25 GNDIO3 30 GPIO3, HS1 GPIO6, DAO2 _DATA0, HS3 31 27 GPIO7, HS4 32 VDD2 GND4 33 28 GPIO9, SCP_MOSI 34 GPIO5, XMTA GPIO10, SCP__MISO / SDA 35 29 GPIO11, SCP_CLK 36 Figure 9-12 shows the 48-Pin LQFP Pin Layout of the CS48520.
Pin Assignments CS485xx Hardware User’s Manual 9.6 Pin Assignments Table 9-9 shows the names and functions for each pin of the CS48560. Table 9-9. Pin Assignments of CS48560 LQFP-48 Pin # 9-17 Function 1 (Default) Description of Default Function Secondary Functions Description of Secondary Functions Pwr Type TEST Test 3.3V (5V tol) 2 RESET Active Low Chip Reset 3.3V (5V tol) IN 3 DBDA Debug Data 3.3V (5V tol) BiDi 4 GNDD1 Core ground 0V PWR 5 DBCK Debug Clock 3.
Pin Assignments CS485xx Hardware User’s Manual Table 9-9. Pin Assignments of CS48560 (Continued) LQFP-48 Pin # 36 Function 1 (Default) GPIO11 Description of Default Function Type Reset State Pullup at Reset BiDi/OD IN Y Secondary Functions Description of Secondary Functions General Purpose Input/Output 1. SCP_CLK 1. SPI/I2C Control Port Clock Pwr 3.3V (5V tol) PWR 37 VDDIO3 I/O power supply voltage 38 GPIO8 General Purpose Input/Output 1. SCP_CS 1. SPI Chip Select 3.3V (5V tol) 3.
Pin Assignments CS485xx Hardware User’s Manual Table 9-10. Pin Assignments of CS48540 (Continued) LQFP-48 Pin # Function 1 (Default) Description of Default Function Type Reset State Pullup at Reset Secondary Functions Description of Secondary Functions Pwr 25 GPIO18 General Purpose Input/Output 1. DAO_MCLK 1. Audio Master Clock 3.3V (5V tol) BiDi IN Y 26 GPIO4 General Purpose Input/Output 1. DAO1_DATA2 2. HS2 1. Digital Audio Output 2. Hardware Strap Mode Select 3.
Pin Assignments CS485xx Hardware User’s Manual Table 9-11. Pin Assignments of CS48520 (Continued) LQFP-48 Pin # 11 Function 1 (Default) GPIO0 Description of Default Function Type Reset State Pullup at Reset IN Y Secondary Functions Description of Secondary Functions Pwr General Purpose Input/Output 3.3V (5V tol) BiDi 12 VDDIO1 I/O power supply voltage 3.3V PWR 13 GPIO1 General Purpose Input/Output 3.3V (5V tol) BiDi IN Y 14 GPIO2 General Purpose Input/Output 3.
Revision History CS485xx Hardware User’s Manual Revision History Revision Date Changes UM1 UM2 December 06 2006 December 11 2006 Preliminary Release Updated with comments from final review. UM3 October 09, 2007 Updated “Single Clock Domain - 12 Channel Input” on page 4. UM4 December 20, 2007 UM5 February 09, 2009 UM6 March 11, 2009 UM7 August 05,, 2009 Updated Type column in pin assignment descriptions found in Table 8-10, Table 8-11, and Table 8-12 for Pins 1 and 3.
Revision History CS485xx Hardware User’s Manual DS734UM7 Copyright 2009 Cirrus Logic, Inc.
