Instruction Manual

DS632F1 15
CS44800
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C
L
=30pF)
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For f
sck
<1 MHz.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency f
sck
0-6.0MHz
CS
High Time between Transmissions t
csh
1.0 - - µs
CS
Falling to CCLK Edge t
css
20 - - ns
CCLK Low Time t
scl
66 - - ns
CCLK High Time t
sch
66 - - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - - ns
CCLK Rising to DATA Hold Time (Note 19) t
dh
15 - - ns
CCLK Falling to CDOUT Stable t
pd
- - 50 ns
Rise Time of CDOUT t
r1
- - 25 ns
Fall Time of CDOUT t
f1
- - 25 ns
Rise Time of CCLK and CDIN (Note 20) t
r2
- - 100 ns
Fall Time of CCLK and CDIN (Note 20) t
f2
- - 100 ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
Figure 9. Control Port Timing - SPI Format