Instruction Manual

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http://www.cirrus.com

DS723F1

JAN ‘13

Low-Power, Stereo Digital-to-Analog Converter

FEATURES

 98 dB dynamic range (A-weighted)

 -86 dB THD+N

 Headphone amplifier–GND centered

– On-chip charge pump provides -VA_HP

– No DC-blocking capacitor required

– 46 mW power into stereo 16  @ 1.8 V

– 88 mW power into stereo 16  @ 2.5 V

– -75 dB THD+N

 Digital signal processing engine

– Bass and treble tone control, de-emphasis

– PCM mix with independent volume control

– Master digital volume control and limiter

– Soft-ramp and zero-cross transitions

 Beep generator

– Tone selections across two octaves

– Separate volume control

– Programmable On and Off time intervals

– Continuous, periodic, or one-shot beep

selections

 Programmable peak-detect and limiter

 Pop and click suppression

SYSTEM FEATURES

 24-bit Conversion

 4- to 96-kHz sample rate

 Multibit delta–sigma architecture

 Low power operation

– Stereo playback: 12.93 mW @ 1.8 V

 Variable power supplies

– 1.8- to 2.5-V digital and analog

– 1.8- to 3.3-V interface logic

 Power-down management

 Software Mode (I²C™ and SPI™ control)

 Hardware mode (standalone control)

 Digital routing/mixes:

– Mono mixes

 Flexible clocking options

– Master or slave operation

– High-impedance digital output option (for

easy MUXing between DAC and other data

sources)

– Quarter-speed mode (allows 8-kHz Fs

while maintaining a flat noise floor up to

16 kHz)

APPLICATIONS

 Portable audio players

 MD players

 PDAs

 Personal media players

 Portable game consoles

 Smart phones

 Wireless headsets

1.8 V to 3.3 V

Multibit

Modulator

Charge

Pump

Left HP Out

Right HP Out

Serial Audio

Input

1.8 V to 2.5 V

PCM Serial Interface

Configuration

Level Translator

Reset

Hardware

Mode or I

C &

SPI Software

Mode

Control Data

Beep

Generator

MUX

Headphone

Amp - GND

Centered

Headphone

Amp - GND

Centered

1.8 V to 2.5 V

Switched

Capacitor DAC

and Filter

Switched

Capacitor DAC

and Filter

Digital

Signal

Processing

Engine

CS43L21

Summary of content (64 pages)

PAGE 1
CS43L21 Low-Power, Stereo Digital-to-Analog Converter  Low power operation FEATURES –  98 dB dynamic range (A-weighted)  Variable power supplies  -86 dB THD+N – –  Headphone amplifier–GND centered – – – – – On-chip charge pump provides -VA_HP No DC-blocking capacitor required 46 mW power into stereo 16  @ 1.8 V 88 mW power into stereo 16  @ 2.5 V -75 dB THD+N  1.8- to 2.5-V digital and analog 1.8- to 3.
PAGE 2
CS43L21 GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies.
PAGE 3
CS43L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ................................................
PAGE 4
CS43L21 6.2 Power Control 1 (Address 02h) ...................................................................................................... 40 6.3 Speed Control (Address 03h) ......................................................................................................... 41 6.4 Interface Control (Address 04h) ..................................................................................................... 42 6.5 DAC Output Control (Address 08h) .............................................
PAGE 5
CS43L21 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 19.Control Port Timing, I²C Write ................................................................................................... 35 Figure 20.Control Port Timing, I²C Read ................................................................................................... 35 Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16  load) ...........
PAGE 6
CS43L21 Pin Name # SDIN SCLK MCLK TSTO(M/S) DGND VD VL RESET 1.
PAGE 7
CS43L21 AOUTB AOUTA 10 11 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table VA 12 Analog Power (Input) - Positive power for the internal analog section. AGND 13 Analog Ground (Input) - Ground reference for the internal analog section. FILT+ 14 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
PAGE 8
CS43L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) I/O Driver Receiver RESET Input - 1.8 V - 3.3 V SCL/CCLK (I²S/LJ) Input - 1.8 V - 3.3 V, with Hysteresis SDA/CDIN (MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis AD0/CS (DEM) Input - 1.8 V - 3.3 V MCLK Input - 1.8 V - 3.3 V LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.
PAGE 9
CS43L21 2. TYPICAL CONNECTION DIAGRAMS See Note 3 +1.8 V or +2.5 V 1 µF 0.1 µF 0.1 µF VD VA 0.1 µF +1.8 V or +2.5 V 1 µF Note 3: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VA_HP AOUTB ** 1.5 µF 1 µF ** AOUTA FLYN 0.022 µF See Note 4 VSS_HP 1.5 µF ** Headphone Out Left & Right FLYP 51.
PAGE 10
CS43L21 See Note 1 +1.8V or +2.5V 1 µF 0.1 µF 0.1 µF VD VA 0.1 µF +1.8V or +2.5V 1 µF Note 1: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VA_HP AOUTB 1 µF ** AOUTA FLYN 1 µF ** Headphone Out Left & Right FLYP 0.022 µF 51.1  VSS_HP GND_HP 470 C * *Use low ESR ceramic capacitors.
PAGE 11
CS43L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters Symbol Min Max Units DC Power Supply (Note 1) VA 1.65 2.63 V VA_HP 1.65 2.63 V Digital Core VD 1.65 2.
PAGE 12
CS43L21 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k CL = 10 pFfor the line output (see Figure 3), and test load RL = 16  CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) VA = 2.5V (nominal) VA = 1.
PAGE 13
CS43L21 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 k CL = 10 pFfor the line output (see Figure 3), and test load RL = 16  CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) VA = 2.5V (nominal) Min Typ Max Parameter (Note 4) VA = 1.
PAGE 14
CS43L21 LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max 1.95 - 2.15 - 1.41 - - - Unit AOUTx Voltage Into RL = 10 k HP_GAIN[2:0] Analog Gain (G) 000 0.3959 001 0.4571 010 0.5111 011 (default) 0.6047 100 0.
PAGE 15
CS43L21 HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16  CL = 10 pF (see Figure 3). VA = 2.5V (nominal) Min Typ Max Parameter VA = 1.8V (nominal) Min Typ Max Unit AOUTx Power Into RL = 16  HP_GAIN[2:0] Analog Gain (G) 000 0.3959 001 0.4571 010 0.5111 011 (default) 0.6047 100 0.7099 101 0.8399 110 1.0000 111 1.
PAGE 16
CS43L21 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 8) Frequency Response 10 Hz to 20 kHz Passband to -0.05 dB corner to -3 dB corner StopBand StopBand Attenuation (Note 9) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Min Typ Max Unit -0.01 - +0.08 dB 0 0 - 0.4780 0.4996 Fs Fs 0.5465 - - Fs 50 - - dB - 10.4/Fs - s - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 dB dB dB Notes: 8. Response is clock dependent and will scale with Fs.
PAGE 17
CS43L21 Parameters Symbol Min Fs - Max Units Master Mode (Note 12) Output Sample Rate (LRCK) All Speed Modes (Note 13) LRCK Duty Cycle 1/tP SCLK Frequency SCLK Duty Cycle MCLK ----------------128 45 55 % - 64•Fs Hz 45 55 % 52 ns td(MSB) LRCK Edge to SDIN MSB Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Hz ts(SD-SK) 20 - ns th 20 - ns 10.
PAGE 18
CS43L21 SWITCHING SPECIFICATIONS - I²C CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
PAGE 19
CS43L21 SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RESET Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.
PAGE 20
CS43L21 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Min Typ Max Units Nominal Voltage Output Impedance DC Current Source/Sink (Note 17) - 0.5•VA 23 - 10 V k A FILT+ - VA - V - -0.8•(VA_HP) 10 V A - 60 - dB VQ Characteristics VSS_HP Characteristics Nominal Voltage DC Current Source Power Supply Rejection Ratio (PSRR) (Note 18) 1 kHz 17.
PAGE 21
CS43L21 POWER CONSUMPTION See (Note 20) Operation 1 Off (Note 21) 2 Standby (Note 22) 5 Mono Playback 6 Stereo Playback Typical Current (mA) PDN_DACB PDN_DACA BIT 4 BIT 3 BIT 2 BIT 1 PDN BIT 3 BIT 2 BIT 1 Power Control Registers 02h 03h iVA_HP iVA iVD iVL (Note 23) V x x x x x x x x x x 1.8 0 0 0 0 0 2.5 0 0 0 0 0 1.8 0 0.01 0.02 0 0.05 2.5 0 0.01 0.03 0 0.10 1 0 1 1 1 1 0 1 1 1 1.8 2.5 1.66 1.40 2.35 0.01 9.74 2.03 1.71 3.48 0.02 18.
PAGE 22
CS43L21 4. APPLICATIONS 4.1 4.1.1 Overview Architecture The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128 Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK). 4.1.
PAGE 23
CS43L21 4.2 Hardware Mode A limited feature-set is available when the D/A powers up in Hardware Mode (see “Recommended PowerUp Sequence” section on page 31) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available.
PAGE 24
CS43L21 4.3 Analog Outputs AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options are available, including an internal Beep Generator. The desired path to the DAC must be selected using the DATA_SEL[1:0] bits. Software Controls: “DAC Control (Address 09h)” on page 43. ARATE[7:0] RRATE[7:0] MAX[2:0] MIN[2:0] LIM_SRDIS LIM_ZCDIS LIMIT_EN SIGNAL PROCESSING ENGINE (SPE) OUTA_VOL[7:0] OUTB_VOL[7:0] +12dB/-102dB 0.5dB steps PCM Serial Interface Chnl Vol.
PAGE 25
CS43L21 Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz Frequency F2 10.61 kHz Figure 9. De-Emphasis Curve 4.3.2 Volume Controls Two digital volume control functions offer independent control of the SDIN signal path into the mixer as well as a combined control of the mixed signals. The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. The signal paths may also be muted via mute control bits.
PAGE 26
CS43L21 REPEAT = '1' BEEP = '1' CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared. REPEAT = '1' BEEP = '0' MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared.
PAGE 27
CS43L21 Input MAX[2:0] Limiter AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled. ATTACK/RELEASE SOUND CUSHION Volume Output (after Limiter) CUSH[2:0] MAX[2:0] ARATE[5:0] RRATE[5:0] Figure 11. Peak Detect & Limiter 4.3.7 Line-Level Outputs and Filtering The device contains on-chip buffer amplifiers capable of producing line level single-ended outputs on AOUTA and AOUTB. These amplifiers are ground centered and do not have any DC offset.
PAGE 28
CS43L21 4.3.8 On-Chip Charge Pump An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency (bass) response. Note: Series resistance in the path of the power supplies must be avoided.
PAGE 29
CS43L21 4.4.1 Slave LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits.
PAGE 30
CS43L21 4.4.3 High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a highimpedance state, allowing another device to transmit clocks without bus contention. CS43L21 Transmitting Device #2 Transmitting Device #1 3ST_SP SCLK/LRCK Receiving Device Figure 13. Tri-State SCLK/LRCK 4.4.
PAGE 31
CS43L21 LRCK L eft C h a n n e l R ig ht C h a n n el SCLK SDIN MSB M SB LS B LS B MSB AOUTB AOUTA Figure 15. Left-Justified Format LRCK L eft C h a n n el R ig ht C h a n n el SCLK MSB SDIN M SB LSB AOUTA LS B AOUTB Figure 16. Right-Justified Format (DAC only) 4.6 Initialization The initialization and Power-Down sequence flowchart is shown in Figure 16 on page 31. The device enters a Power-Down state upon initial power-up.
PAGE 32
CS43L21 4.8 Recommended Power-Down Sequence To minimize audible pops when turning off or placing the device in standby, 1. Mute the DACs. 2. Disable soft ramp and zero cross volume transitions. 3. Set the PDN bit to 1. 4. Wait at least 100 µs. The DAC will be fully powered down after this 100 µs delay. Prior to the removal of the master clock (MCLK), this delay of at least 100 µs must be implemented after step 3 to avoid premature disruption of the device’s power down sequence.
PAGE 33
CS43L21 No Power 1. No audio signal generated. Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default. PDN bit = '1'b? Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings. Yes No No RESET = Low? Valid MCLK Applied? Yes No 20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged. Initialization 50 ms delay No Control Port Valid Write Seq.
PAGE 34
CS43L21 4.9 Software Mode The control port is used to access the registers allowing the D/A to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
PAGE 35
CS43L21 operation is a read, the contents of the register pointed to by the MAP will be output. Setting the autoincrement bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS43L21 after each input byte is read and is input to the CS43L21 from the microcontroller after each transmitted byte.
PAGE 36
CS43L21 4.9.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.9.3.1 Map Increment (INCR) The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes.
PAGE 37
CS43L21 5. REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state. Addr 01h Function ID p 40 default 02h Power Ctl. 1 p 40 7 6 5 4 3 2 1 0 Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0 1 1 0 1 1 0 0 1 Reserve Reserved Reserved Reserved PDN Reserved PDN_DACB PDN_DACA Speed Ctl. & Power Ctl. 2 p 41 default 04h Interface Ctl.
PAGE 38
CS43L21 Addr 10h Function Vol. Control PCMMIXA p 45 default 11h Vol. Control PCMMIXB p 45 default 12h BEEP Freq. & OnTime p 46 default 13h BEEP Off Time & Vol p 46 default 14h BEEP Control & Tone Config p 48 default 15h Tone Control p 49 default 16h Vol. Control AOUTA p 49 default 17h Vol.
PAGE 39
CS43L21 Addr Function 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Status Reserved SP_CLK ERR Reserved Reserved p 53 default 0 0 0 0 0 0 0 0 CHRG_ FREQ3 CHRG_ FREQ2 CHRG_ FREQ1 CHRG_ FREQ0 Reserved Re
PAGE 40
CS43L21 6. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All “Reserved” registers must maintain their default state. 6.1 Chip I.D.
PAGE 41
CS43L21 Function: The entire D/A will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode. 6.3 Speed Control (Address 03h) 7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 Reserved 2 Reserved 1 Reserved 0 MCLKDIV2 Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the D/A when operating as a slave.
PAGE 42
CS43L21 6.4 Interface Control (Address 04h) 7 Reserved 6 M/S 5 DAC_DIF2 4 DAC_DIF1 3 DAC_DIF0 2 Reserved 1 Reserved 0 Reserved Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port.
PAGE 43
CS43L21 These bits select the gain multiplier for the headphone/line outputs. See “Line Output Voltage Characteristics” on page 14 and “Headphone Output Power Characteristics” on page 15. DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled.
PAGE 44
CS43L21 This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. Notes: 1. This bit should only be used to synchronize run-time controls, such as volume and mute, during normal operation.
PAGE 45
CS43L21 Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing.
PAGE 46
CS43L21 6.8 Beep Frequency & Timing Configuration (Address 12h) 7 FREQ3 6 FREQ2 5 FREQ1 4 FREQ0 3 ONTIME3 2 ONTIME2 1 ONTIME1 0 ONTIME0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Frequency (FREQ[3:0]) Default: 0000 FREQ[3:0] Frequency Pitch Fs = 12, 24, 48 or 96 kHz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 260.87 Hz 521.74 Hz 585.37 Hz 666.67 Hz 705.88 Hz 774.19 Hz 888.89 Hz 1000.
PAGE 47
CS43L21 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 OFFTIME[2:0] Off Time Fs = 12, 24, 48 or 96 kHz 000 001 010 011 100 101 110 111 1.23 s 2.58 s 3.90 s 5.20 s 6.60 s 8.05 s 9.35 s 10.80 s Function: The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode.
PAGE 48
CS43L21 6.10 Beep Configuration & Tone Configuration (Address 14h) 7 REPEAT 6 BEEP 5 Reserved 4 TREB_CF1 3 TREB_CF0 2 BASS_CF1 1 BASS_CF0 0 TC_EN Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Repeat Beep (REPEAT) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output.
PAGE 49
CS43L21 Tone Control Enable (TC_EN) Default = 0 0 - Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled. 6.11 Tone Control (Address 15h) 7 TREB3 6 TREB2 5 TREB1 4 TREB0 3 BASS3 2 BASS2 1 BASS1 0 BASS0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Treble Gain Level (TREB[3:0]) Default: 1000 dB (No Treble Gain) Binary Code Gain Setting 0000 ··· 0111 1000 1001 ··· 1111 +12.
PAGE 50
CS43L21 AOUTA (Address 16h) & AOUTB (Address 17h) 7 6 5 4 3 2 1 0 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. AOUTX Volume Control (AOUTX_VOL[7:0]) Default = 00h Binary Code Volume Setting 0001 1000 ··· 0000 0000 1111 1111 1111 1110 ··· 0011 0100 ··· 0001 1001 +12.0 dB ··· 0 dB -0.5 dB -1.
PAGE 51
CS43L21 6.14 Limiter Threshold SZC Disable (Address 19h) 7 MAX2 6 MAX1 5 MAX0 4 CUSH2 3 CUSH1 2 CUSH0 1 LIM_SRDIS 0 LIM_ZCDIS Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30 Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate.
PAGE 52
CS43L21 Limiter Soft Ramp Disable (LIM_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = ‘01’b or ‘11’b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting.
PAGE 53
CS43L21 Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Binary Code Release Time 000000 ··· 111111 Fastest Release ··· Slowest Release Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
PAGE 54
CS43L21 Signal Processing Engine Overflow (SPEX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path after the signal processing engine. PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM mix. 6.
PAGE 55
CS43L21 7. ANALOG PERFORMANCE PLOTS 7.1 Headphone THD+N versus Output Power Plots Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB43L21 using an Audio Precision analyzer. G = 0.6047 -10 -15 VA_HP = VA = 1.8 V G = 0.7099 -20 G = 0.8399 -25 -30 G = 1.0000 -35 G = 1.1430 -40 -45 d B r A Legend NOTE: Graph shows the output power per channel (i.e.
PAGE 56
CS43L21 G = 0.6047 -20 G = 0.7099 VA_HP = VA = 1.8 -30 G = 0.8399 -35 G = 1.0000 -40 -45 G = 1.1430 -50 Legend NOTE: Graph shows the output power per channel (i.e. Output Power = 22 mW into single 32  and 44 mW into stereo 32  with THD+N = 75 dB). -55 d B r -60 A -65 -70 -75 -80 -85 -90 -95 -100 0 6m 12m 18m 24m 30m 36m 42m 48m 54m 60m W Figure 23. THD+N vs. Output Power per Channel at 1.8 V (32  load) G = 0.6047 -20 -25 G = 0.7099 VA_HP = VA = 2.5 V -30 G = 0.
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CS43L21 7.2 Headphone Amplifier Efficiency The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback with 16- load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power. VA_HP = VA = 1.8 V Figure 25. Power Dissipation vs. Output Power into Stereo 16  VA_HP = VA = 1.8 V Figure 26. Power Dissipation vs.
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CS43L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 1024x MCLK (MHz) 1536x 2048x* 8 11.025 12 3072x* 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 512x MCLK (MHz) 768x 1024x* 16 22.05 24 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 16.3840 22.5792 24.5760 Sample Rate LRCK (kHz) MCLK (MHz) 384x 512x* 256x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.
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CS43L21 8.2 Auto Detect Disabled DS723F1 Sample Rate LRCK (kHz) 512x 8 11.025 12 6.1440 768x MCLK (MHz) 1024x 1536x 2048x 3072x 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 256x 384x 512x 16 22.05 24 6.1440 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 MCLK (MHz) 768x 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 256x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.
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CS43L21 9. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS43L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead.
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CS43L21 10.DIGITAL FILTERS DS723F1 Figure 27. Passband Ripple Figure 28. Stopband Figure 29. Transition Band Figure 30.
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CS43L21 11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement.
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CS43L21 13.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING e b D Pin #1 Corner Pin #1 Corner E2 E A1 L D2 A Top View DIM MIN A A1 b D D2 E E2 e L -0.0000 0.0071 0.1280 0.1280 0.0118 Bottom View Side View INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157 MAX MIN 0.0394 0.0020 0.0110 -0.00 0.18 0.1319 3.25 0.1319 3.25 0.0197 0.30 MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40 NOTE MAX 1.00 0.05 0.28 3.35 3.35 0.
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CS43L21 14.ORDERING INFORMATION Product CS43L21 CDB43L21 Description Package Pb-Free Grade Temp Range Commercial -10 to +70° C Low-Power Stereo D/A with HP Amp for Portable Apps 32L-QFN CS43L21 Evaluation Board - Yes No Automotive -40 to +85° C - - Container Order # Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR - CDB43L21 15.REVISION HISTORY Revision F1 Changes Updated voltage range in “Specified Operating Conditions” on page 11.