User Manual

DS568F1 13
CS4398
LRCK
SCLK
Left Channel
Right Channel
SDATA +3 +2 +1 LSB +5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB +5 +4
MSB -1 -2 -3 -4
Figure 3. Format 0 - Left-Justified up to 24-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDATA +3 +2 +1 LSB +5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB +5 +4
MSB -1 -2 -3 -4
Figure 4. Format 1 - I²S up to 24-bit Data
LRCK
SCLK
Left Channel
SDATA
+5
+4 +3 +2
+1
LSB
MSB -1 -2 -3 -4 -5
32 clocks
Right Channel
LSB +5
+4 +3 +2
+1
LSB
MSB
-1 -2 -3 -4
-5
+6
-6
+6
-6
Figure 5. Format 2, Right-Justified 16-Bit Data.
Format 3, Right-Justified 24-Bit Data.
Format 4, Right-Justified 20-Bit Data. (Available in Control Port Mode only)
Format 5, Right-Justified 18-Bit Data. (Available in Control Port Mode only)