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CS4397

24-Bit, Multi-Standard D/A Converter for Digital Audio

Features

24 Bit Conversion

Up to 192 kHz Sample Rates

120 dB Dynamic Range

-100 dB THD+N

Supports PCM, DSD and External

Interpolation filters

Advanced Dynamic-Element Matching

Low Clock Jitter Sensitivity

Digital De-emphasis for 32 kHz, 44.1 kHz and

48 kHz

External Reference Input

Description

The CS4397 is a complete high performance 24-bit

48/96/192 kHz stereo digital-to-analog conversion sys-

tem. The device includes a digital interpolation filter

followed by a oversampled multi-bit delta-sigma modula-

tor which drives dynamic-element-matching (DEM)

selection logic. The output from the DEM block controls

the input to a multi-element switched capacitor DAC/low-

pass filter, with fully-differential outputs. This multi-bit ar-

chitecture features significantly lower out-of-band noise

and jitter sensitivity than traditional 1-bit designs, and the

advanced DEM guarantees low noise and distortion at

all signal levels.

ORDERING INFORMATION

CS4397-KS -10° to 70° C 28-pin Plastic SOIC

CS4397-KSZ -10° to 70° C 28-pin Plastic SOIC Lead free

CDB4397 Evaluation Board

SCLK

MCLK

LRCK

SDATA

AOUTL+

AOUTR+

SERIAL INTERFACE

AND FORMAT SELECT

INTERPOLATION

SOFT MUTE

∆Σ

MODULATOR

DYNAMIC

DE-EMPHASIS

SWITCHED

AOUTL-

AOUTR-

FILT+

FILTER

INTERPOLATION

FILTER

MULTI-BIT

∆Σ

MODULATOR

MULTI-BIT

ELEMENT

MATCHING

LOGIC

DYNAMIC

ELEMENT

MATCHING

LOGIC

CAPACITOR-DAC

AND FILTER

SWITCHED

CAPACITOR-DAC

AND FILTER

VREF CMOUTFILT-

VOLTAGE REFERENCE

HARDWARE MODE CONTROL

CLOCK

DIVIDER

(CONTROL PORT)

(AD0/CS)

M3 M2

(AD1/CDIN) (SCL/CCLK)

(SDA/CDOUT)

RESET MUTEC MUTE

SEP ‘04

DS333F1

Summary of content (34 pages)

PAGE 1
CS4397 24-Bit, Multi-Standard D/A Converter for Digital Audio Features Description 24 Bit Conversion Up to 192 kHz Sample Rates 120 dB Dynamic Range -100 dB THD+N Supports PCM, DSD and External Interpolation filters Advanced Dynamic-Element Matching Low Clock Jitter Sensitivity Digital De-emphasis for 32 kHz, 44.1 kHz and 48 kHz External Reference Input The CS4397 is a complete high performance 24-bit 48/96/192 kHz stereo digital-to-analog conversion system.
PAGE 2
CS4397 TABLE OF CONTENTS 1.0 CHARACTERISTICS/SPECIFICATIONS ..................................................................... 4 ANALOG CHARACTERISTICS................................................................................... 4 Dynamic Performance - Single Speed Mode - Fs equal to 48 kHz ...................... 4 Dynamic Performance - Double Speed Mode - Fs equal to 96 kHz .................... 4 Dynamic Performance - Quad-Speed Mode - Fs equal to 192 kHz .....................
PAGE 3
CS4397 TABLE OF FIGURES Figure 1. Serial Audio Input Timing ......................................................................... 10 Figure 2. Direct Stream Digital - Serial Audio Input Timing ..................................... 11 Figure 3. Serial Audio Input Timing ......................................................................... 12 Figure 4. I2C Control Port Timing ............................................................................ 13 Figure 5. SPI Control Port Timing .............
PAGE 4
CS4397 1.0 CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = DGND; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
PAGE 5
CS4397 ANALOG CHARACTERISTICS (Continued) Parameter Power Supplies Supply Current VA = 5 V Symbol normal operation normal operation power-down state Power Dissipation VA = 5 V IA ID ID + IA normal operation power-down Power Supply Rejection Ratio (1 kHz) (Note 3) (120 Hz) Parameter PSRR Symbol Analog Output Full Scale Differential Output Voltage Common Mode Voltage VD = 3 V Unit VD = 5 V Min Typ Max Min Typ Max - 20 TBD 60 TBD TBD - - 20 TBD 30 TBD TBD - mA mA µA - TBD 0.
PAGE 6
CS4397 ANALOG CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Unit - - 0.470 0.492 Fs Fs -.020 - +0.015 dB - - ±0.0001 dB Combined Digital and On-chip Analog Filter Response - Single Speed Mode Passband (Note 4) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz Passband Ripple StopBand StopBand Attenuation (Note 5) Group Delay (Note 6) De-emphasis Error tgd (Note 7) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz (Relative to 1 kHz) .
PAGE 7
CS4397 ANALOG CHARACTERISTICS - DSD MODE (TA = 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
PAGE 8
CS4397 ANALOG CHARACTERISTICS - 8X INTERPOLATOR MODE (TA = 25 °C; Logic "1" = VD = 5 V; VA = 5V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; Base Band Fs = 48 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
PAGE 9
CS4397 DIGITAL CHARACTERISTICS (TA = 25°C; VD = 3.0V - 5.25V) Parameters High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance Maximum MUTEC Drive Current VD = 5 V VD = 3 V VD = 5 V VD = 3 V Symbol VIH VIL Iin Min 2.0 2.0 - Typ 8 3 Max 0.8 0.8 ±10 - Units V V V V µA pF mA ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.
PAGE 10
CS4397 SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = 5.25 to 3.
PAGE 11
CS4397 DSD - SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = 5.25 to 3.
PAGE 12
CS4397 8X INTERPOLATOR - SWITCHING CHARACTERISTICS (TA= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = 5.25 to 3.0 Volts; CL = 20 pF) Parameter Input Sample Rate MCLK Frequency (Note 10) (MCLK = 32×Fs) (MCLK = 48×Fs) (MCLK = 64×Fs) (MCLK = 96×Fs) MCLK Duty Cycle WCKI Duty Cycle BCKI Frequency BCKI rising to WCKI edge delay BCKI rising to WCKI edge setup time SDATA valid to BCKI rising setup time BCKI rising to DIL/DIR hold time Symbol Fs Min 128 4.096 6.144 8.192 12.
PAGE 13
CS4397 SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 KHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
PAGE 14
CS4397 SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF) Parameter Symbol Min Max Unit CCLK Clock Frequency fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
PAGE 15
CS4397 2.0 TYPICAL CONNECTION DIAGRAM +5 to +3 V Digital + 1 µF 0.1 µ F 5 Mode Select (Control Port) 14 4 3 2 16 0.1 µf +1.0 µ F 7 8 VD VD M0 (SDA/CDOUT) 22 VA VREF FILT+ 11 Audio Data Processor 27 FILT- 26 C/H CMOUT CS4397 12 0.1 µf M3 (AD1/CDIN) M4 (AD0/CS) LRCK AOUTL- +5V Analog 28 M1 (GND) M2 (SCL/CCLK) +5V Analog 0.1 µf + 100 µf 0.1 µf 5.
PAGE 16
CS4397 3.0 REGISTER DESCRIPTION 3.1 DIFFERENTIAL DC OFFSET CALIBRATION Mode Control Register (address 01h) 7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN Access: R/W in I2C and SPI. Default: 0 - Disabled Function: Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be automatically reset following completion of the calibration sequence. CAL 0 1 MODE Disabled : CAL complete Enabled : CAL initiated Table 1. 3.
PAGE 17
CS4397 3.3 MODE SELECT Mode Control Register (address 01h) 7 CAL 6 MUTE 5 M4 4 M3 3 M2 2 M1 1 M0 0 PDN Access: R/W in I2C and SPI. Default: 00000 Function: The Mode Select pins determine the operational mode of the device as detailed in Tables 9-14.
PAGE 18
CS4397 4.
PAGE 19
CS4397 Sample Rate (kHz) 32 44.1 48 256x 8.1920 11.2896 12.2880 MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 768x 24.5760 33.8688 36.8640 Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 64 88.2 96 128x 8.1920 11.2896 12.2880 MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 384x 24.5760 33.8688 36.8640 Table 5. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) 176.
PAGE 20
CS4397 cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias voltage on the outputs will be retained and MUTEC will go active at the completion of the ramp period. The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The MUTEC will release immediately on setting MUTE = 1.
PAGE 21
CS4397 Common Mode Voltage - CMOUT Pin 25, Output Function: Filter connection for internal bias voltage, typically 50% of VREF. Capacitors must be connected from CMOUT to analog ground, as shown in Figure 6. CMOUT has a typical source impedence of 25 kΩ and any current drawn from this pin will alter device performance Reference Ground - FILT- Pin 26, Input Function: Ground reference for the internal sampling circuits. Must be connected to analog ground.
PAGE 22
CS4397 Address Bit 1 / Control Data Input - AD1/CDIN Pin 3, Input Function: In I2C mode, AD1 is a chip address bit. CDIN is the control data input line for the control port interface in SPI mode. Serial Control Interface Clock - SCL/CCLK Pin 4, Input Function: In I2C mode, SCL clocks the serial control data into or from SDA/CDOUT. In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT.
PAGE 23
CS4397 5.
PAGE 24
CS4397 6.
PAGE 25
CS4397 7.0 APPLICATIONS 7.1 Recommended Power-up Sequence 1. Hold RST low until the power supplies, master, and left/right clocks are stable. 2. Bring RST high.
PAGE 26
CS4397 8.0 CONTROL PORT INTERFACE The control port is used to load all the internal settings of the CS4397. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4397 operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VD or DGND.
PAGE 27
CS4397 CS CCLK CHIP ADDRESS CDIN 0010000 MAP R/W DATA LSB MSB byte 1 byte n MAP = Memory Address Pointer = 0 Figure 7. Control Port Timing, SPI mode Note 1 SDA 001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK SCL Start Stop Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 8.
PAGE 28
CS4397 M4 0 0 0 0 M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION FORMAT FIGURE 0 1 2 3 29 30 31 33 Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Table 9. Single Speed (16 to 50 kHz) Digital Interface Format Options M4 0 0 0 0 M3 (DEM1) 0 0 1 1 M2 (DEM0) 0 1 0 1 DESCRIPTION 32 kHz De-Emphasis 44.1 kHz De-Emphasis 48 kHz De-Emphasis De-Emphasis Disabled FIGURE 28 28 28 - Table 10.
PAGE 29
0 0 -20 -20 -40 -40 Amplitude dB Amplitude dB CS4397 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 0.460.47 0.48 0.480.49 0.50.50 0.56 0.580.59 0.6 0.6 0.45 0.46 0.51 0.520.52 0.53 0.540.54 0.55 0.56 0.57 0.58 -160 0.45 0.5 0.55 0.6 0 0.1 -1 0.08 -2 0.06 -3 0.04 -4 -5 -6 -7 0.8 0.85 0.9 0.95 1 0 -0.02 -0.04 -8 -0.06 -9 -0.08 -0.1 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (normalized to Fs) Figure 11.
PAGE 30
0 0 -20 -20 -40 -40 Amplitude dB Amplitude dB CS4397 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 0.5 0.52 0.54 0.56 Frequency (normalized to Fs) 0 0.1 -1 0.08 -2 0.06 -3 0.04 -4 -5 -6 -7 0.66 0.68 0.7 0 -0.04 -8 -0.06 -9 -0.08 -0.1 0.37 0.39 0.41 0.43 0.45 0.47 0.49 0.51 0.53 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (normalized to Fs) Figure 20.
PAGE 31
0 0 -10 -10 -20 -20 -30 -30 Amplitude dB Amplitude dB CS4397 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 0 1 2 3 4 5 6 7 8 9 10 2.5 Frequency (normalized to Fs) 3 3.5 4 4.5 5 5.5 6 Frequency (normalized to Fs) Figure 25. DSD Frequency Response Figure 26. DSD Transition Band Gain dB 0 -1 Amplitude dB -2 T1=50 µs -3 0dB -4 -5 -6 T2 = 15 µs -7 -8 -10dB -9 -10 0 0.5 1 1.5 2 2.5 3 Frequency (normalized to Fs) Figure 27.
PAGE 32
CS4397 Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 29. Format 0, Left Justified Left Channel LRCK Right Channel SCLK SDATA MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 Figure 30. Format 1, I2S LRCK Right Channel Left Channel SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Figure 31.
PAGE 33
CS4397 9.0 PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
PAGE 34
CS4397 11.0 PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c ∝ D L SEATING PLANE A e A1 DIM A A1 B C D E e H L ∝ INCHES MIN 0.093 0.004 0.013 0.009 0.697 0.29G10 1 0.040 0.394 0.016 0° MAX 0.104 0.012 0.020 0.013 0.713 0.299 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 0.060 0.419 0.050 8° 1.02 10.00 0.40 0° 1.52 10.65 1.