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Preliminary Product Information

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CS4391A

24-Bit, 192 kHz Stereo DAC with Volume Control

Features

Complete Stereo DAC System: Interpolation,

D/A, Output Analog Filtering

108 dB Dynamic Range

94 dB THD+N

Direct Stream Digital Mode

Low Clock Jitter Sensitivity

+5 V Power Supply

ATAPI Mixing

On-Chip Digital De-emphasis for 32, 44.1,

and 48 kHz

Volume Control with Soft Ramp

– 119 dB Attenuation

– 1 dB Step Size

– Zero Crossing Click-Free Transitions

Direct Interface with 5 V to 1.8 V Logic

Description

The CS4391A is a complete stereo digital-to-analog sys-

tem including digital interpolation, fourth-order delta-

sigma digital-to-analog conversion, digital de-emphasis,

volume control, channel mixing and analog filtering. The

advantages of this architecture include: ideal differential

linearity, no distortion mechanisms due to resistor

matching errors, no linearity drift over time and tempera-

ture and a high tolerance to clock jitter.

The CS4391A accepts PCM data at sample rates from

4 kHz to 192 kHz, DSD audio data, consumes very little

power and operates over a wide power supply range.

These features are ideal for DVD, A/V receivers, CD and

set-top box systems.

ORDERING INFORMATION

CS4391A-KS 20-pin SOIC -10 to 70 °C

CS4391A-KZ 20-pin TSSOP -10 to 70 °C

CS4391A-KZZ 20-pin TSSOP, Lead Free -10 to 70 °C

CDB4391A Evaluation Board

LRCK

SDATA

(SDA/CDIN)

MCLK

AMUTEC

AOUTA-

AOUTB-

SERIAL

PORT

INTERPOLATION

INTERPOLATOR

(CONTROL PORT)

∆Σ

DAC

EXTERNAL

ANALOG

FILTER

ANALOG

FILTER

∆Σ

MUTE CONTROL

FILTER

RST

SCLK

VOLUME

CONTROL

VOLUME

CONTROL

MIXER

(SCL/CCLK) (AD0/CS)

AOUTA+

AOUTB+

CMOUT

REFERENCE

FILT+BMUTEC

MODE SELECT

JUL ‘04

DS600PP3

Summary of content (40 pages)

PAGE 1
CS4391A 24-Bit, 192 kHz Stereo DAC with Volume Control Features Description Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering 108 dB Dynamic Range 94 dB THD+N Direct Stream Digital Mode Low Clock Jitter Sensitivity +5 V Power Supply ATAPI Mixing On-Chip Digital De-emphasis for 32, 44.
PAGE 2
CS4391A TABLE OF CONTENTS 1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 5 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 13 3. REGISTER QUICK REFERENCE .......................................................................................... 15 3.1 Mode Control 1 (address 01h) ..........................................................................................
PAGE 3
CS4391A 5. PIN DESCRIPTION - PCM DATA MODE ............................................................................... 22 6. PIN DESCRIPTION - DSD MODE .......................................................................................... 26 7. APPLICATIONS ..................................................................................................................... 33 7.1 Recommended Power-up Sequence for Hardware Mode ............................................... 33 7.
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CS4391A LIST OF FIGURES Figure 1. Serial Mode Input Timing ................................................................................................. 9 Figure 2. Direct Stream Digital - Serial Audio Input Timing ........................................................... 10 Figure 3. I2C Control Port Timing .................................................................................................. 11 Figure 4. SPI Control Port Timing ............................................................
PAGE 5
CS4391A 1. CHARACTERISTICS/SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25 °C, VA = 5.0 V) SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters DC Power Supply Specified Temperature Range Symbol VA VL -KS & -KZ TA Min 4.75 1.8 -10 Typ 5.0 - Max 5.
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CS4391A ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; Test load RL = 5 kΩ, CL = 10 pF) VA = 5 V Parameter Symbol Min Typ Max Unit 100 103 - 105 108 102 - dB dB dB - -94 -85 -45 -89 -40 dB dB dB - 108 - dB - 100 - dB - 17 60 35 - mA µA - 85 0.
PAGE 7
CS4391A ANALOG CHARACTERISTICS (continued) Parameter Symbol Min Typ Max Combined Digital and On-chip Analog Filter Response - Single Speed Mode Passband (Note 3) to -0.05 dB corner 0 .4535 to -3 dB corner 0 .4998 Frequency Response 10 Hz to 20 kHz -.02 +.035 StopBand .5465 StopBand Attenuation (Note 5) 50 Group Delay tgd 9/Fs Passband Group Delay Deviation 0 - 20 kHz ±0.36/Fs De-emphasis Error (Relative to 1 kHz) Control Port Mode Fs = 32 kHz +.2/-.1 Fs = 44.1 kHz +.05/-.14 Fs = 48 kHz +0/.
PAGE 8
CS4391A DIGITAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.
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CS4391A SWITCHING CHARACTERISTICS - PCM MODES Parameters Symbol Input Sample Rate (Inputs: Logic 0 = 0 V, Logic 1 = VL) Min Fs Typ Max Units 4 - 200 kHz LRCK Duty Cycle 45 50 55 % MCLK Duty Cycle 40 50 60 % SCLK Frequency - - MCLK/2 Hz - - MCLK/4 Hz SCLK Frequency (Note 6) SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDATA valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDATA hold time
PAGE 10
CS4391A SWITCHING CHARACTERISTICS - DSD Parameter (Logic 0 = AGND = DGND; Logic 1 = VL) Symbol Min 40 Typ 50 Max 60 Unit % SCLK Pulse Width Low SCLK Pulse Width High SCLK Period tsclkl tsclkh tsclkw 20 20 20 - - ns ns ns SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tsdlrs tsdh 20 20 - - ns ns MCLK Duty Cycle t sclkh t sclkl S C LK t s dlrs t sd h S D A TA Figure 2.
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CS4391A SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 KHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
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CS4391A SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) Parameter Symbol Min Max Unit CCLK Clock Frequency fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
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CS4391A 2. TYPICAL CONNECTION DIAGRAMS 0.1 µf 10 Mode S elect 9 (Control Port) * 8 7 + 1.0 µ f +5V Analog 17 VA M 0 (A D 0/C S ) M 1 (S DA / C D IN ) FILT+ 11 M2 (SCL/CCLK) 0.1 µf + 1.0 µf M3 C S4 391A Logic Power +5V to 1.8V 2 A OU T A- VL 0.1 µf AMUTEC 20 5 Au dio D ata P ro cessor * 19 4 3 1 6 A O UT A + 18 LR CK A na log C onditioning & M ute S C LK A OU T B- S D AT A 14 BM U T EC 13 RST AO U TB + 15 A na log C onditioning & M ute CMOUT 12 M C LK AG N D 16 + 1.
PAGE 14
CS4391A 0.1 µf +1.0 µ f +5V Analog 17 VA 10 M 0 (A D0 /C S ) M o de S e le ct 9 M 1 (S D A/ C DIN ) (Control Port) 8 M 2 (SC L /C C LK ) FILT + 11 0.1 µf + 1.0 µ f CS4391A Lo gic Pow e r +5V to 1.8V 2 0.1 µ f 5 7 A u dio D ata P ro ce ssor * 4 3 A OU T AVL 19 AMUTEC 20 DSD_MODE A O UT A + 1 8 D SD _ C LK D SD _B A OU T B- 14 D S D _A B M U TE C 1 3 1 6 A na lo g C on d itionin g & M ute RST A OUTB+ 15 M CL K A na log C on d ition in g & M u te CMOUT 1 2 AG N D 16 + 1.
PAGE 15
CS4391A 3. REGISTER QUICK REFERENCE ** “default” ==> bit status after power-up-sequence or reset** 3.1 MODE CONTROL 1 (ADDRESS 01H) 7 AMUTE 1 6 DIF2 0 5 DIF1 0 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0 AMUTE (Auto-mute) Default = ‘1’. 0 - Disabled 1 - Enabled DIF2, DIF1 and DIF0 (Digital Interface Format - PCM Modes). See Table 1 Default = ‘0’.
PAGE 16
CS4391A 3.2 VOLUME AND MIXING CONTROL (ADDRESS 02H) 7 A=B 0 6 Soft 1 5 Zero Cross 0 4 ATAPI4 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1 A = B (Channel A Volume = Channel B Volume) Default = ‘0’. 0 - AOUTA volume is determined by register 03h and AOUTB volume is determined by register 04h. 1 - AOUTA and AOUTB volumes are determined by register 03h and register 04h is ignored. Soft & Zero Cross (Soft control and zero cross detection control) Default = ‘10’.
PAGE 17
CS4391A 3.5 MODE CONTROL 2 (ADDRESS 05H) 7 INVERT_A 0 6 INVERT_B 0 5 CPEN 1 4 PDN 1 3 MUTEC A = B 0 2 FREEZE 0 1 MCLK Divide 0 0 Reserved 0 INVERT_A (Invert Channel A) Default = ‘0’. 0 - Disabled 1 - Enabled INVERT_B (Invert Channel B) Default = ‘0’. 0 - Disabled 1 - Enabled CPEN (Control Port Enable) Default = ‘0’ 0 - Disabled (Stand-Alone Mode) 1 - Enabled (Control Port Mode) PDN (Power-Down) Default =’1’. 0 - Disabled 1 - Enabled MUTEC A=B Default = ‘0’.
PAGE 18
CS4391A 4. REGISTER DESCRIPTION ** All register access is R/W in I2C mode and write only in SPI mode ** 4.1 MODE CONTROL 1 - ADDRESS 01H 7 AMUTE 4.1.1 6 DIF2 5 DIF1 4 DIF0 3 DEM1 2 DEM0 1 FM1 0 FM0 Auto-Mute (Bit 7) Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel.
PAGE 19
CS4391A 4.2 VOLUME AND MIXING CONTROL (ADDRESS 02H) 7 A=B 4.2.1 6 Soft 5 Zero Cross 4 ATAPI4 3 ATAPI3 2 ATAPI2 1 ATAPI1 0 ATAPI0 Channel A Volume = Channel B Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled. 4.2.
PAGE 20
CS4391A 4.4 CHANNEL B VOLUME CONTROL - ADDRESS 04H 7 MUTE 4.4.1 6 VOL6 5 VOL5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0 Mute (Bit 7) Function: The Digital-to-Analog converter output will mute when enabled. The common mode voltage on the output will be retained. The muting function is effected, similiar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The MUTEC pin for that channel will go active during the mute period if the Mute function is enabled.
PAGE 21
CS4391A 4.5.5 Freeze (Bit 2) Function: This function allows modifications to the registers without the changes being taking effect until Freeze is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the Freeze Bit, make all register changes, then Disable the Freeze bit. 4.5.6 Master Clock Divide (Bit 1) Function: This function allows the user to select an internal divide by 2 of the Master Clock.
PAGE 22
CS4391A 5.
PAGE 23
CS4391A Serial Clock - SCLK Pin 4, Input Function: Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte in Control Port Mode or the Mode pins in Hardware Mode. The options are detailed in Figures 7-24. Left / Right Clock - LRCK Pin 5, Input Function: The Left / Right clock determines which channel is currently being input on the serial audio data input, SDATA.
PAGE 24
CS4391A Serial Control Interface Clock - SCL/CCLK (Control Port Mode) Pin 8, Input Function: Clocks the serial control data into or from SDA/CDIN. Serial Control Data I/O - SDA/CDIN (Control Port Mode) Pin 9, Input/Output Function: In I2C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Address Bit / Chip Select - AD0 / CS (Control Port Mode) Pin 10, Input Function: In I2C mode, AD0 is a chip address bit.
PAGE 25
CS4391A Differential Analog Output - AOUTB+, AOUTB- and AOUTA+, AOUTAPins 14, 15 and 18, 19, Outputs Function: The full scale differential analog output level is specified in the Analog Characteristics specifications table. Analog Ground - AGND Pin 16, Input Function: Analog ground reference. Analog Power - VA Pin 17, Input Function: Analog power supply.
PAGE 26
CS4391A 6.
PAGE 27
CS4391A DIF2 0 0 DIF1 0 0 DIFO 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Right Justified, 24-bit Right Justified, 20-bit Right Justified, 18-bit Reserved Reserved Data Data Data Data Table 1.
PAGE 28
CS4391A ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+
PAGE 29
CS4391A Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled. Sample Rate (kHz) MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 256x 8.1920 11.2896 12.2880 32 44.1 48 See Note 1024x 32.7680 45.1584 49.1520 768x 24.5760 33.8688 36.8640 Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies Sample Rate (kHz) MCLK (MHz) 192x 256x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 128x 8.1920 11.2896 12.2880 64 88.
PAGE 30
CS4391A M3 1 1 M2 1 1 M1 0 0 M0 0 1 1 1 1 1 1 1 0 1 DESCRIPTION Left Justified up to 24-bit data I2S up to 24-bit data Right Justified 16-bit data Right Justified 24-bit data FORMAT 0 1 FIGURE 7 8 2 3 9 10 Table 14.
PAGE 31
CS4391A L eft C ha n n el LRC K R igh t C ha n n el SC L K SDATA M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 7. Format 0, Left Justified up to 24-Bit Data L eft C ha n n el LRC K R igh t C ha n n el SC L K SDATA MS B -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 8.
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CS4391A LR C K R ig h t C h a n n e l L e ft C h a n n e l SCLK SDATA 1 0 1 9 1 8 17 16 15 14 1 3 1 2 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 3 2 cloc Figure 11. Format 4, ksRight Justified 20-Bit Data. (Available in Control Port Mode only) LR CK R ig h t C h a n ne l L eft C h a nn e l SCLK SDATA 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Figure 12.
PAGE 33
CS4391A 7. APPLICATIONS 7.1 lowing the release of RST. 4) The desired register settings can be loaded while keeping the PDN bit set to 1. Recommended Power-up Sequence for Hardware Mode 5) Set the PDN bit to 0 which will initiate the power-up sequence which requires approximately 10 µS. 1) Hold RST low until the power supplies, master, and left/right clocks are stable. 2) Bring RST high. 7.2 7.
PAGE 34
CS4391A 8. CONTROL PORT INTERFACE The control port is used to load all the internal settings of the CS4391A. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4391A operating as a slave device in both modes. If I2C operation is desired, AD0/CS should be tied to VA or AGND.
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CS4391A 7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 INCR (Auto MAP Increment Enable) Default = ‘0’. 0 - Disabled 1 - Enabled MAP0-2 (Memory Address Pointer) Default = ‘000’. Table 16. Memory Address Pointer (MAP) CS CCLK C H IP ADDRESS C DIN 0 01 00 0 0 MAP DATA MSB R/W b yte 1 LS B b yte n M AP = M e m ory Ad d re ss P o in te r Figure 16.
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CS4391A 0.25 0.2 0.15 Amplitude dB 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) Figure 18. Single-Speed Frequency Response Figure 19. Single-Speed Transition Band Figure 20. Single-Speed Transition Band Figure 21. Single-Speed Stopband Rejection 0.25 0.2 0.15 Amplitude dB 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) Figure 22.
PAGE 37
CS4391A Figure 24. Double-Speed Transition Band DS600PP3 Figure 25.
PAGE 38
CS4391A 9. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
PAGE 39
CS4391A 11.PACKAGE DIMENSIONS 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E A ∝ e b2 SIDE VIEW A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0° INCHES NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4° MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8° MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0° MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4° NOTE MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.
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CS4391A PACKAGE DIMENSIONS(cont.). 20L SOIC (300 MIL BODY) PACKAGE DRAWING E H 1 b c ∝ D L SEATING PLANE A e DIM A A1 b C D E e H L ∝ MIN 0.093 0.004 0.013 0.009 0.496 0.291 0.040 0.394 0.016 0° A1 INCHES NOM 0.098 0.008 0.017 0.011 0.504 0.295 0.050 0.407 0.025 4° MAX 0.104 0.012 0.020 0.013 0.512 0.299 0.060 0.419 0.050 8° MIN 2.35 0.10 0.33 0.23 12.60 7.40 1.02 10.00 0.40 0° MILLIMETERS NOM 2.50 0.20 0.43 0.28 12.80 7.50 1.27 10.34 0.64 4° MAX 2.65 0.30 0.51 0.32 13.00 7.60 1.52 10.