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114-dB, 192-kHz 8-Channel D/A Converter

Features

 Advanced Multi-bit Delta Sigma Architecture

 24-bit Conversion

 Automatic Detection of Sample Rates up to

192 kHz

 114 dB Dynamic Range

 -100 dB THD+N

 Direct Stream Digital

(DSD) Mode

– Non-decimating Volume Control

– On-chip 50 kHz Filter

– Matched PCM and DSD Analog Output Levels



Compatible with Industry-standard Time

Division Multiplexed (TDM) Serial Interface in

both Hardware and Software Modes

 Selectable Digital Filters

 Volume Control with 1/2 dB Step Size and Soft

Ramp

 Low Clock-jitter Sensitivity

 +5 V Analog Supply, +2.5 V Digital Supply

 Separate 1.8 to 5 V Logic Supplies for the

Control & Serial Ports

Description

The CS4385A is a complete 8-channel digital-to-analog

system. This D/A system includes digital de-emphasis,

half-dB step size volume control, ATAPI channel mix-

ing, selectable fast and slow digital interpolation filters

followed by an oversampled, multi-bit delta sigma mod-

ulator which includes mismatch-shaping technology

that eliminates distortion due to capacitor mismatch.

Following this stage is a multi-element switched capac-

itor stage and low-pass filter with differential analog

outputs.

The CS4385A also has a proprietary DSD processor

that allows for volume control and 50 kHz on-chip filter-

ing without an intermediate decimation stage. It also

offers an optional path for direct DSD conversion by di-

rectly using the multi-element, switched capacitor array.

The CS4385A is available in a 48-pin LQFP package in

both Commercial (-40°C to +85°C) and Automotive

(-40°C to +105°C) grades. Please see “Ordering Infor-

mation” on page 53 for complete details.

The CS4385A accepts PCM data at sample rates from

4 kHz to 216 kHz, Direct Stream Digital

audio data, and

delivers excellent sound quality. These features are ide-

al for multi-channel audio systems, including SACD

players, A/V receivers, digital TV’s, mixing consoles, ef-

fects processors, sound cards, and automotive audio

systems.

Control Port Supply = 1.8 V to 5 V

Configuration

Internal Voltage

Reference

Reset

Serial Interface

Level TranslatorLevel Translator

TDM Serial

Audio Input

Digital Supply = 2.5 V

Hardware Mode or

C/SPI Software Mode

Control Data

Analog Supply = 5 V

Eight Channels

of Differential

Outputs

PCM Serial

Audio Input

Volume

Controls

Digital

Filters

Switch-Cap

DAC and

Analog Filters

Multi-bit

Modulators

DSD Audio

Input

DSD Processor

-Volume control

-50 kHz filter

External Mute

Control

Mute Signals

Serial Audio Port

Supply = 1.8 V to 5 V

APRIL '14

DS837F2

CS4385A

Summary of content (55 pages)

PAGE 1
CS4385A 114-dB, 192-kHz 8-Channel D/A Converter Features Description  Advanced Multi-bit Delta Sigma Architecture The CS4385A is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator which includes mismatch-shaping technology that eliminates distortion due to capacitor mismatch.
PAGE 2
CS4385A TABLE OF CONTENTS 1. PIN DESCRIPTION .............................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8 ABSOLUTE MAXIMUM RATINGS .................................................................
PAGE 3
CS4385A 7.1.2 Chip Revision [Read Only] .................................................................................................... 37 7.2 Mode Control 1 (Address 02h) ....................................................................................................... 37 7.2.1 Control Port Enable (CPEN) .................................................................................................. 37 7.2.2 Freeze Controls (FREEZE) ..............................................................
PAGE 4
CS4385A LIST OF FIGURES Figure 1.TDM Serial Audio Interface Timing ............................................................................................. 15 Figure 2.Serial Audio Interface Timing ...................................................................................................... 15 Figure 3.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16 Figure 4.
PAGE 5
CS4385A LIST OF TABLES Table 1. Single-Speed Mode (SSM) Standard Frequencies ..................................................................... 21 Table 2. Double-Speed Mode (DSM) Standard Frequencies ................................................................... 21 Table 3. Quad-Speed Mode (QSM) Standard Frequencies ...................................................................... 21 Table 4. PCM Digital Interface Format, Hardware Mode Options ..................................................
PAGE 6
CS4385A AOUTB1- MUTEC1 AOUTA1AOUTA1+ AOUTB1+ DSDA4 DSDB4 VLS DSD_SCLK DSDB2 DSDA3 DSDB3 1.
PAGE 7
CS4385A Pin Name AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,- # Pin Description 39, 40 38, 37 35, 36 34, 33 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the 29, 30 Analog Characteristics specification table. 28, 27 25, 26 24, 23 VA 32 Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.
PAGE 8
CS4385A 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters Symbol Min Typ Max Units Analog power Digital internal power Serial data port interface power Control port interface power Ambient Operating Temperature (Power Applied) Commercial Grade (-CQZ) Automotive Grade (-DQZ) VA VD VLS VLC 4.75 2.30 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.70 5.25 5.
PAGE 9
CS4385A DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-scale 997 Hz input sine wave (Note 1); Tested under maximum AC-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
PAGE 10
CS4385A DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V; VD = 2.37 to 2.63 V; TA = -40°C to 85°C; Full-scale 997 Hz input sine wave (Note 1); Tested under maximum ACload resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
PAGE 11
CS4385A POWER AND THERMAL CHARACTERISTICS Parameters Symbol Min Typ Max Units normal operation, VA= 5 V VD= 2.5 V (Note 5) Interface current, VLC=5 V VLS=5 V (Note 6) power-down state (all supplies) Power Dissipation (Note 4) VA = 5 V, VD = 2.
PAGE 12
CS4385A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See Note 12. Fast Roll-Off Parameter Unit Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response to -0.
PAGE 13
CS4385A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) Slow Roll-Off (Note 8) Parameter Unit Min Typ Max 0 0 - 0.417 0.499 Fs Fs -0.01 - +0.01 dB .583 - - Fs 64 - - dB Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) - 7.8/Fs - s Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - ±0.36 ±0.21 ±0.
PAGE 14
CS4385A DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-Level Input Voltage Min Typ Max Units Iin 8 - ±10 0.30•VLS 0.30•VLC 0.20•VLC A pF V V V V V Serial I/O Control I/O Serial I/O Control I/O Control I/O = 3.3 V, 5 V VIH VIH VIL VIL VOL 0.70•VLS 0.70•VLC - Low-Level Output Voltage (IOL = -1.2 mA) Control I/O = 1.8 V, 2.5 V VOL - - 0.
PAGE 15
CS4385A SWITCHING CHARACTERISTICS - PCM Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF. Parameters Symbol RST pin Low Pulse Width (Note 14) MCLK Frequency MCLK Duty Cycle (Note 15) Min Max Units 1 - ms 1.024 55.
PAGE 16
CS4385A SWITCHING CHARACTERISTICS - DSD Logic 0 = GND; Logic 1 = VLS; CL = 20 pF. Parameter Symbol MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation Mode) tsdlrs tsdh tdpm Min Typ Max Unit 40 160 160 1.024 2.048 20 20 -20 - 60 3.2 6.
PAGE 17
CS4385A SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF. Symbol Min Max Unit SCL Clock Frequency Parameter fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
PAGE 18
CS4385A SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF. Symbol Min Max Unit CCLK Clock Frequency Parameter fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
PAGE 19
CS4385A 3. TYPICAL CONNECTION DIAGRAM +2.5 V 1 µF + 4 VD 32 VA AOUTA1+ AOUTA1AOUTB1+  6 7 9 PCM Digital Audio Source 8 11 13 14 AOUTB1- MCLK LRCK AOUTA2+ SCLK AOUTA2- SDIN1 SDIN2 AOUTB2+ SDIN3 AOUTB2- SDIN4  AOUTA3+ 43 +1.8 V to +5 V VLS 0.
PAGE 20
CS4385A +2.5 V 1 µF + 4 VD 32 VA AOUTA1+ AOUTA1AOUTB1+  6 7 PCM Digital Audio Source 9 8 11 13 14  43 +1.8 V to +5 V AOUTB1- MCLK 3 2 1 48 DSD Audio Source 47 46 45 44 42 Optional 47 K 10 12 Hardware Stand-Alone Mode Mode Configuration Configuration 15 16 17 19 39 40 38 +5 V 1 µF Analog Conditioning and Muting 37 Analog Conditioning and Muting 41 Mute Drive LRCK SCLK MUTEC1 SDIN1 SDIN2 SDIN3 AOUTA2+ SDIN4 AOUTA2AOUTB2+ VLS AOUTB2CS4385A CS4385 0.1 µF  + 0.
PAGE 21
CS4385A 4. APPLICATIONS The CS4385A serially accepts two’s complement formatted PCM data. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutorial,” available at www.cirrus.com.
PAGE 22
CS4385A 4.2 Mode Select In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continually scanned for any changes; however, the mode should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode to another. These pins require connection to supply or ground as outlined in Figure 8. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS. Tables 4 - 6 show the decode of these pins.
PAGE 23
CS4385A 4.3 Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and TDM digital interface formats with varying bit depths from 16 to 32, as shown in Figures 9-18. Data is clocked into the DAC on the rising edge. OLM configuration is only supported in Software Mode. Left Channel LRCK Right Channel SCLK SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 9.
PAGE 24
CS4385A 4.3.1 OLM #1 OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1. The last two channels are input on SDIN4.
PAGE 25
CS4385A 4.3.4 OLM #4 OLM #4 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on SDIN1. LRCK 128 clks 128 clks Left Channel Right Channel SCLK MSB SDIN1 LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB DAC_A1 DAC_A2 DAC_A3 DAC_A4 DAC_B1 DAC_B2 DAC_B3 DAC_B4 24 clks 24 clks 24 clks 24 clks 24 clks 24 clks 24 clks 24 clks MSB Figure 17.
PAGE 26
CS4385A 4.5 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4385A incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in each of the three speed modes, Single-, Double-, and Quad-Speed. These filters have been designed to accommodate a variety of musical tastes and styles.
PAGE 27
CS4385A 4.7 ATAPI Specification The CS4385A implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 on page 46 and Figure 20 for additional information. A Channel Volume Control Left Channel Audio Data  SDINx Right Channel Audio Data MUTE Aout Ax MUTE AoutBx  B Channel Volume Control Figure 20. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) 4.
PAGE 28
CS4385A DSD Phase Modulation Mode DSD Normal Mode BCKA (64Fs) Not Used DSD_SCLK BCKA (128Fs) DSD_SCLK DSD_SCLK BCKD (64Fs) Not Used DSDAx, DSDBx D0 D1 D1 D0 D1 D2 D2 DSDAx, DSDBx Not Used Figure 21. DSD Phase Modulation Mode Diagram 4.9 Grounding and Power Supply Arrangements As with any high-resolution converter, the CS4385A requires careful attention to power supply and grounding arrangements if optimal potential performance levels are to be realized.
PAGE 29
CS4385A 4.10 Analog Output and Filtering Cirrus Logic application note AN55, “Design Notes for a 2-Pole Filter with Differential Input,” discusses the second-order Butterworth filter and differential-to-single-ended converter shown in Figure 23. The CS4385A does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response are dependent on the external analog circuitry.
PAGE 30
CS4385A 4.11 The MUTEC Outputs The MUTEC1 and MUTEC234 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4385A will detect the status of the MUTEC pins (high or low) and then select that state as the polarity to drive when the mutes become active.
PAGE 31
CS4385A 4.12.2 Software Mode 1. Hold RST low until the power supply is stable and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. 2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode). 3.
PAGE 32
CS4385A 5. CONTROL PORT INTERFACE The control port is used to load all the internal register settings in order to operate in Software Mode (see Section 7. “Register Description” on page 37). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I²C or SPI. 5.
PAGE 33
CS4385A 2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP, or the default address (see Section 5.1) if an I²C read is the first operation performed on the device. 3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4.
PAGE 34
CS4385A CS CCLK CHIP ADDRESS C DIN 0011000 MAP DATA LSB MSB R/W byte 1 byte n M AP = M em ory Address Pointer Figure 26. Control Port Timing, SPI Mode 5.4 Memory Address Pointer (MAP) 7 INCR 0 5.4.1 6 Reserved 0 5 Reserved 0 4 MAP4 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0 INCR (Auto Map Increment Enable) Default = ‘0’ 0 - Disabled 1 - Enabled 5.4.
PAGE 35
CS4385A 6.
PAGE 36
CS4385A Addr 14h 15h 16h 36 Function 7 Vol. Control A4 A4_VOL7 default 0 Vol.
PAGE 37
CS4385A 7. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 7.1 Chip I.D. and Revision (Address 01h) 7 6 5 4 3 2 1 0 CHIPID4 1 CHIPID3 0 CHIPID2 0 CHIPID1 0 CHIPID0 1 REV2 - REV1 - REV0 - 7.1.1 Chip I.D. [Read Only] 10001- CS4385A 7.1.2 Chip Revision [Read Only] 010 - Revision B1 Function: This read-only register can be used to identify the model and revision number of the device. 7.
PAGE 38
CS4385A 7.2.3 PCM/DSD Selection (DSD/PCM) Default = 0 0 - PCM 1 - DSD Function: This function selects DSD or PCM Mode. The appropriate data and clocks should be present before changing modes, or else MUTE should be selected. 7.2.4 DAC Pair Disable (DACx_DIS) Default = 0 0 - DAC Pair x Enabled 1 - DAC Pair x Disabled Function: When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
PAGE 39
CS4385A DIF3 DIF2 DIF1 DIF0 0 0 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 0 0 0 0 X 0 0 1 1 0 0 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 X DESCRIPTION FORMAT Left-Justified, up to 24-bit data I²S, up to 24-bit data Right-Justified, 16-bit data TDM Right-Justified, 20-bit data Right-Justified, 18-bit data One-Line Mode 1, 24-bit Data +SDIN4 One-Line Mode 2, 20-bit Data +SDIN4 0 1 2 3 4 5 8 9 10 11 One-Line Mode 3, 24-bit 6-channel One-Line Mode 4, 20-bit 6-channel All other combinations are Reserved Table 7.
PAGE 40
CS4385A DIF2 DIF1 DIFO 1 1 1 1 0 0 1 1 0 1 0 1 DESCRIPTION 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 8. Digital Interface Formats - DSD Mode 7.4.2 Direct DSD Conversion (DIR_DSD) Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions.
PAGE 41
CS4385A 7.5 Filter Control (Address 05h) 7 6 5 4 3 2 1 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 FILT_SEL 0 7.5.1 Interpolation Filter Select (FILT_SEL) Function: When set to 0 (default), the Interpolation Filter has a fast roll-off. When set to 1, the Interpolation Filter has a slow roll-off. The specifications for each filter can be found in the Analog characteristics table, and response plots can be found in Figures 27 to 50. 7.
PAGE 42
CS4385A 7.7.2 Channel A Volume = Channel B Volume (Px_A=B) Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled. 7.7.
PAGE 43
CS4385A Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 7.8.
PAGE 44
CS4385A 7.8.6 Mute Polarity and Detect (MUTEP1:0) Default = 00 00 - Auto polarity detect, selected from MUTEC1 pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity Function: Auto mute polarity detect (00) See Section 4.11 “The MUTEC Outputs” on page 30 for description. Active low mute polarity (10) When RST is low, the outputs are high impedance and will need to be biased active.
PAGE 45
CS4385A 7.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) 7 6 5 4 3 2 1 0 Reserved 0 Px_DEM1 0 Px_DEM0 0 PxATAPI4 0 PxATAPI3 1 PxATAPI2 0 PxATAPI1 0 PxATAPI0 1 7.10.1 De-Emphasis Control (PX_DEM1:0) Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates (see Figure 19). De-emphasis is only available in Single-Speed Mode.
PAGE 46
CS4385A 7.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4385A implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 and Figure 20 for additional information.
PAGE 47
CS4385A 7.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) 7 6 5 4 3 2 1 0 xx_VOL7 0 xx_VOL6 0 xx_VOL5 0 xx_VOL4 0 xx_VOL3 0 xx_VOL2 0 xx_VOL1 0 xx_VOL0 0 These eight registers provide individual volume and mute control for each of the eight channels.
PAGE 48
CS4385A 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 8. FILTER PLOTS −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 27. Single-Speed (fast) Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 28. Single-Speed (fast) Transition Band 0.02 0 −1 0.015 −2 0.01 −3 0.005 Amplitude (dB) Amplitude (dB) −4 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.
PAGE 49
CS4385A 0.02 0 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 Figure 33. Single-Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 34. Single-Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.4 0.
PAGE 50
CS4385A 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 39. Double-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 40. Double-Speed (slow) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.
PAGE 51
CS4385A 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 45. Quad-Speed (fast) Transition Band (detail) 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 46. Quad-Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.
PAGE 52
CS4385A 9. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
PAGE 53
CS4385A 10.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B  A A1 L DIM MIN INCHES NOM MAX MIN MILLIMETERS NOM MAX A A1 B D D1 E E1 e* L µ --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.
PAGE 54
CS4385A 12.REFERENCES 1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note AN48. 3. The I²C-Bus Specification: Version 2.0, Philips Semiconductors, December 1998. http://www.semiconductor.philips.
PAGE 55
CS4385A 13.REVISION HISTORY Release Changes F1 Changed to Final Release AUG ‘08 F2 Updated Section 6 and Section 7.6, “Invert Control (Address 06h),” to show register configuration for TDM Mode. APR ‘14 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc.