Owner's manual

DS620F1 21
CS4384
4.2 Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST
pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in Figure 8. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS.
Tables 4 - 6 show the decode of these pins.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “PCM
Control (Address 03h)” on page 36.
M1
(DIF1)
M0
(DIF0)
DESCRIPTION FORMAT FIGURE
00
Left Justified, up to 24-bit data
0 9
01
I
2
S, up to 24-bit data
1 10
10
Right Justified, 16-bit Data
2 11
11
Right Justified, 24-bit Data
3 12
Table 4. PCM Digital Interface Format, Hardware Mode Options
M4 M3 M2
(DEM)
M1 M0 DESCRIPTION
000
Table 4
Single-Speed without De-Emphasis (4 kHz to 50 kHz sample rates)
001
Single-Speed with 44.1 kHz De-Emphasis; see Figure 20
010
Double-Speed (50 kHz to 100 kHz sample rates)
011
Quad-Speed (100 kHz to 200 kHz sample rates)
100
Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates)
101
Auto Speed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 20
11 Table 6
DSD Processor Mode
Table 5. Mode Selection, Hardware Mode Options
M2 M1 M0 DESCRIPTION
000
64x oversampled DSD data with a 4x MCLK to DSD data rate
001
64x oversampled DSD data with a 6x MCLK to DSD data rate
010
64x oversampled DSD data with a 8x MCLK to DSD data rate
011
64x oversampled DSD data with a 12x MCLK to DSD data rate
100
128x oversampled DSD data with a 2x MCLK to DSD data rate
101
128x oversampled DSD data with a 3x MCLK to DSD data rate
110
128x oversampled DSD data with a 4x MCLK to DSD data rate
111
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Direct Stream Digital (DSD), Hardware Mode Options