CS4382A 114 dB, 192 kHz 8-Channel D/A Converter Features Description Advanced Multi-bit Delta Sigma Architecture The CS4382A is a complete 8-channel digital-to-analog system. This D/A system includes digital de-emphasis, 1 dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta-sigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch.
CS4382A TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ...............................................................
CS4382A 6.2.1 Digital Interface Format (DIF) ................................................................................................ 34 6.3 Mode Control 3 (Address 03h) ....................................................................................................... 35 6.3.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 35 6.3.2 Single Volume Control (SNGLVOL) ................................................................
CS4382A LIST OF FIGURES Figure 1.Serial Audio Interface Timing ...................................................................................................... 15 Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16 Figure 3.Control Port Timing - I²C Format ................................................................................................. 17 Figure 4.Control Port Timing - SPI Format .......................
CS4382A LIST OF TABLES Table 1. Common Clock Frequencies ....................................................................................................... 21 Table 2. Digital Interface Format, Stand-Alone Mode Options .................................................................. 22 Table 3. Mode Selection, Stand-Alone Mode Options .............................................................................. 22 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options .......................
CS4382A AOUTB1- AOUTB1+ AOUTA1+ AOUTA1- MUTEC1 M3(DSD_SCLK) DSDB4 VLS DSDA4 DSDB3 DSDA3 DSDB2 1.
CS4382A Pin Name AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,- # Pin Description 39, 40 38, 37 35, 36 34, 33 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the 29, 30 Analog Characteristics specification table. 28, 27 25, 26 24, 23 VA 32 Analog Power (Input) - Positive power supply for the analog section.
CS4382A 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters Symbol Min Typ Max Units Analog Power Digital Internal Power Serial Data Port Interface Power Control Port Interface Power Ambient Operating Temperature (power applied) Commercial Grade (-CQZ) Automotive Grade (-DQZ) VA VD VLS VLC 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.
CS4382A DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-Scale 997 Hz input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
CS4382A DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V; VD = 2.37 to 2.63 V; TA = -40°C to 85°C; Full-Scale 997 Hz input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
CS4382A POWER AND THERMAL CHARACTERISTICS Parameters Symbol Min Typ Max Units Normal Operation, VA= 5 V VD= 2.5 V (Note 5) Interface Current, VLC=5 V VLS=5 V (Note 6) Power-down State (all supplies) Power Dissipation (Note 4) VA = 5 V, VD = 2.
CS4382A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See Note 12. Fast Roll-Off Parameter Min Typ Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response Stop Band Stop-band Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) to -0.
CS4382A COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) Slow Roll-Off (Note 8) Min Typ Max Parameter Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 10 Hz to 20 kHz Frequency Response Stop Band Stop-band Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) (Note 10) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Unit 0 0 -0.01 .583 64 - 7.8/Fs - 0.417 0.499 +0.01 ±0.36 ±0.21 ±0.14 Fs Fs dB Fs dB s dB dB dB 0 0 -0.01 .792 70 - 5.4/Fs .
CS4382A DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-level Input Voltage Low-level Input Voltage Low-level Output Voltage (IOL = -1.2 mA) Maximum MUTEC Drive Current MUTEC High-level Output Voltage MUTEC Low-level Output Voltage (Note 13) Serial I/O Control I/O Serial I/O Control I/O Control I/O = 3.3 V, 5 V Control I/O = 1.8 V, 2.
CS4382A SWITCHING CHARACTERISTICS - PCM (Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters Symbol Min Max Units 1 - ms 1.024 55.
CS4382A SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS; CL = 20 pF) Parameter Symbol MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time tsdlrs tsdh Min Typ Max Unit 40 160 160 1.024 2.048 20 20 - 60 3.2 6.4 - % ns ns MHz MHz ns ns t sclkh t sclkl DSD_SCLK t sdlrs t sdh DSDxx Figure 2.
CS4382A SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Symbol Min Max Unit SCL Clock Frequency Parameter fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
CS4382A SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Symbol Min Max Unit CCLK Clock Frequency Parameter fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
CS4382A 3. TYPICAL CONNECTION DIAGRAM +2.5 V +5 V 1 µF + 0.
CS4382A +2.5 V +5 V 1 µF + 0.1 µF 0.
CS4382A 4. APPLICATIONS The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48, 44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
CS4382A M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION FORMAT FIGURE 0 1 2 3 Figure 7 Figure 8 Figure 9 Figure 10 Left-justified, up to 24-bit data I²S, up to 24-bit data Right-justified, 16-bit Data Right-justified, 24-bit Data Table 2. Digital Interface Format, Stand-Alone Mode Options M3 0 0 1 1 M2 (DEM) 0 1 0 1 DESCRIPTION Single-speed without De-emphasis (4 to 50 kHz sample rates) Single-speed with 44.
CS4382A 4.3 Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-justified, and Right-justified digital interface formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the rising edge. Left Channel LRCK Right Channel SCLK SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 7.
CS4382A LRCK Right Channel Left Channel SCLK SDINx 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0 32 clocks Figure 11. Format 4 - Right-Justified 20-bit Data LRCK Right Channel Left Channel SCLK SDINx 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 32 clocks Figure 12. Format 5 - Right-Justified 18-bit Data 4.
CS4382A In Software Mode, the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected via the de-emphasis control bits. In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected, the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual Fs over 44,100. Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 13.
CS4382A 4.8 Direct Stream Digital (DSD) Mode In Stand-alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio. In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held high). The DIF register then controls the expected DSD rate and MCLK ratio.
CS4382A 3.85 V 2.5 V AOUT+ 1.15 V 3.85 V AOUT- 2.5 V 1.15 V Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp Figure 15. Full-Scale Output Figure 16. Recommended Output Filter 4.11 Mute Control The Mute Control pins go active during power-up initialization, muting, or if the MCLK-to-LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any single-ended, single-supply system.
CS4382A Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Figure 17. Recommended Mute Circuitry 4.12 Recommended Power-Up Sequence 4.12.1 Hardware Mode 1.
CS4382A 4.13 Recommended Procedure for Switching Operational Modes For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources). The mute bits may then be released after clocks have settled and the proper modes have been set. It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met during clock source changes. 4.
CS4382A 4.14.2.2 I²C Read To read from the device, follow the procedure below while adhering to the Control Port Switching Specifications. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP.
CS4382A 6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high. CS C C LK C H IP ADDRESS C DIN 0011000 MAP D A TA LSB MSB R /W byte 1 byte n M A P = M em ory A ddress P ointe r Figure 19. Control Port Timing, SPI Mode 4.15 Memory Address Pointer (MAP) 7 INCR 0 4.
CS4382A 5. REGISTER QUICK REFERENCE Addr Function 7 01h Mode Control 1 default Mode Control 2 default Mode Control 3 default Filter Control default Invert Control default Mixing Control Pair 1 (AOUTx1) default Vol. Control A1 default Vol. Control B1 default Mixing Control Pair 2 (AOUTx2) default Vol. Control A2 default Vol. Control B2 default Mixing Control Pair 3 (AOUTx3) default Vol. Control A3 default Vol. Control B3 default Mixing Control Pair 4 (AOUTx4) default Vol. Control A4 default Vol.
CS4382A 6. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Mode Control 1 (Address 01h) 7 CPEN 0 6.1.1 6 FREEZE 0 5 MCLKDIV 0 4 DAC4_DIS 0 3 DAC3_DIS 0 2 DAC2_DIS 0 1 DAC1_DIS 0 0 PDN 1 Control Port Enable (CPEN) Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1.
CS4382A 6.1.5 Power Down (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port Mode can occur. 6.2 Mode Control 2 (Address 02h) 7 Reserved 0 6.2.
CS4382A DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required master clock-to-DSD-data-rate is defined by the Digital Interface Format pins.
CS4382A 6.3.2 Single Volume Control (SNGLVOL) Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled. 6.3.
CS4382A 6.3.6 Mutec Pin Control (MUTEC) Default = 0 0 - Two Mute control signals 1 - Single mute control signal on MUTEC1 Function: Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’, a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234.
CS4382A from mute to the original volume value after a filter-mode change according to the settings of the Soft and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is performed. Loss of clocks or a change in the FM bits will always cause an immediate mute; unmute in these conditions is affected by the RMP_UP bit. Note: 6.5 Invert Control (Address 05h) 7 INV_B4 0 6.5.
CS4382A 6.6.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
CS4382A 6.6.3 Functional Mode (FM) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the same functional mode setting before a speed-mode change is accepted. When DSD Mode is selected for any channel pair, all pairs switch to DSD Mode. 6.
CS4382A 6.7.2 Volume Control (XX_VOL) Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling the MUTE bit.
CS4382A 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 7. FILTER PLOTS −60 −60 −80 −80 −100 −100 −120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 −120 0.4 1 Figure 20. Single-Speed (fast) Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 21. Single-Speed (fast) Transition Band 0.02 0 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.
CS4382A 0.02 0 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 Figure 26. Single-Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 27. Single-Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.
CS4382A 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 32. Double-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 33. Double-Speed (slow) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.
CS4382A 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 38. Quad-Speed (fast) Transition Band (detail) 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 39. Quad-Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.
CS4382A 8. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
CS4382A 9. PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L DIM MIN INCHES NOM MAX MIN MILLIMETERS NOM MAX A A1 B D D1 E E1 e* L µ --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.
CS4382A 10.ORDERING INFORMATION Product Description Package Pb-Free CS4382A 114 dB, 192 kHz 8channel D/A Converter 48-pin LQFP CDB4382A CS4382A Evaluation Board YES - Grade Temp Range Container Tray Commercial -40°C to +85°C Tape & Reel Tray Automotive -40°C to +105°C Tape & Reel - Order # CS4382A-CQZ CS4382A-CQZR CS4382A-DQZ CS4382A-DQZR CDB4382A 11.REFERENCES 1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris.
CS4382A 12.REVISION HISTORY Release PP1 PP2 F1 F2 DS618F2 Changes Updated output impedance spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10. Improved interchannel isolation spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10. Corrected package type. Corrected register description in “DAC Pair Disable (DACx_DIS)” on page 33. Added note to “Digital Interface Format (DIF)” on page 34. Added PCM mode format changeable in reset only to “Mode Select” on page 21.
CS4382A Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).
