CS4382 114 dB, 192 kHz 8-Channel D/A Converter Features Description 24-bit Conversion The CS4382 is a complete 8-channel digital-to-analog system including digital interpolation, fifth-order deltasigma digital-to-analog conversion, digital de-emphasis, volume control and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter.
CS4382 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 5 ANALOG CHARACTERISTICS............................................................................................................. 5 ANALOG CHARACTERISTICS............................................................................................................. 6 POWER AND THERMAL CHARACTERISTICS ...........................................................
CS4382 6.2 PCM Mode Select ......................................................................................................................... 28 6.3 Recommended Power-Up Sequence ........................................................................................... 28 6.4 Analog Output and Filtering .......................................................................................................... 28 6.5 Interpolation Filter ................................................................
CS4382 Figure 28. Quad-Speed (fast) Passband Ripple ........................................................................................ 36 Figure 29. Quad-Speed (slow) Stopband Rejection................................................................................... 36 Figure 30. Quad-Speed (slow) Transition Band......................................................................................... 36 Figure 31. Quad-Speed (slow) Transition Band (detail)............................................
CS4382 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test load RL = 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5) For Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz; For Double-Speed Mode, Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz; For Quad-Speed Mode, Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.
CS4382 ANALOG CHARACTERISTICS (Continued) Parameters Analog Output - All PCM modes and DSD Full Scale Differential Output Voltage Quiescent Voltage Max Current from VQ Interchannel Gain Mismatch Gain Drift Output Impedance AC-Load Resistance Load Capacitance (Note 4) (Note 4) Symbol Min Typ Max Units VFS VQ IQMAX 86% VA - 91% VA 50% VA 1 96% VA - Vpp VDC μA ZOUT RL CL 3 - 0.
CS4382 ANALOG FILTER RESPONSE Fast Roll-Off Slow Roll-Off (Note 10) Parameter Min Typ Max Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode (Note 11) Passband (Note 12) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay Passband Group Delay Deviation 0 - 20 kHz De-emphasis Error (Note 14) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.
CS4382 DIGITAL CHARACTERISTICS (For KQZ TA = -10°C to +70°C; VLC = VLS = 1.8 V to 5.
CS4382 SWITCHING CHARACTERISTICS (For KQZ TA = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF) Parameters Symbol Min Typ Max Units 1.024 - 51.2 MHz Double-Speed Mode 6.400 - 51.2 MHz Quad-Speed Mode 6.400 - 51.
CS4382 DSD - SWITCHING CHARACTERISTICS (For KQZ TA = -10°C to +70°C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL = 30 pF) Parameter Symbol Master Clock Frequency (Note 18) MCLK Duty Cycle (All DSD modes) DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency (64x Oversampled) (128x Oversampled) DSD_L / _R valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_L or DSD_R hold time tsclkl tsclkh tsdlrs tsdh Min Typ Max Unit 4.096 40 50 38.4 60 MHz % 20 20 1.
CS4382 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT (For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Symbol Min Max Unit SCL Clock Frequency Parameter fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.
CS4382 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF) Parameter Symbol Min Max Unit fsclk - MCLK ----------------2 MHz tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
CS4382 2. TYPICAL CONNECTION DIAGRAM +5 V + 3 .3 V to + 5 V + 1 µF 0 .1 µ F 0 .1 µ F 4 VD A O U TA 1- 7 9 PCM D ig ita l A u d io S o u rc e 10 12 8 11 13 14 M C LK AO UTB1+ LRC K1 A O U TB 1- + 1 .
CS4382 + 3 .3 V to + 5 V +5 V + 1 µF VLS N o te D S D 4 VD 47 K Ω AO U TA1- 7 9 PCM D ig ita l A u d io S o u rc e 10 12 8 11 13 14 43 + 1 .
CS4382 3. REGISTER QUICK REFERENCE Addr Function 01h Mode Control 1 02h Mode Control 2 03h Mode Control 3 04h Filter Control 05h Invert Control 06h Mixing Control Pair 1 (AOUTx1) 07h Vol. Control A1 08h Vol. Control B1 default default default default default default default default 09h Mixing Control Pair 2 (AOUTx2) default 0Ah Vol. Control A2 default 0Bh Vol. Control B2 default 0Ch Mixing Control Pair 3 (AOUTx3) default 0Dh Vol. Control A3 default 0Eh Vol.
CS4382 4. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write-only in SPI, unless otherwise noted. 4.1 Mode Control 1 (Address 01h) 7 CPEN 0 4.1.1 6 FREEZE 0 5 MCLKDIV 0 4 DAC4_DIS 0 3 DAC3_DIS 0 2 DAC2_DIS 0 1 DAC1_DIS 0 0 PDN 1 Control Port Enable (CPEN) Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can be accessed by setting this bit to 1.
CS4382 4.1.5 Power Down (PDN) Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port Mode can occur. 4.2 Mode Control 2 (Address 02h) 7 Reserved 0 4.2.
CS4382 DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins. An additional write of 99h to register 00h and 80h to register 1Ah is required to access the modes denoted with *.
CS4382 Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing.
CS4382 4.3.5 Auto-Mute (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period.
CS4382 Selects the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 39) De-emphasis is only available in Single-Speed Mode. 4.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Default = 0 0 - Disabled 1 - Enabled Function: A mute will be performed prior to executing a filter mode change.
CS4382 4.6.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information.
CS4382 4.6.3 Functional Mode (FM) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode. When DSD Mode is selected for any channel pair then all pairs will switch to DSD Mode. 4.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h) 7 xx_MUTE 0 4.7.
CS4382 4.8 Chip Revision (Address 12h) 7 PART3 1 4.8.1 6 PART2 0 5 PART1 1 4 PART0 0 3 Reserved - 2 Reserved - 1 Reserved - 0 Reserved - Part Number ID (PART) [Read Only] 1010 - CS4382 Function: This read-only register can be used to identify the model number of the device.
CS4382 AOUTB1- AOUTA1+ AOUTB1+ MUTEC1 AOUTA1- VLS M3(DSD_SCLK) DSDB4 DSDA4 DSDB3 DSDB2 DSDA3 5.
CS4382 Pin Name MUTEC1 MUTEC234 AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,- # Pin Description 41 22 Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system.
CS4382 Mode (sample-rate range) MCLK Ratio Single-Speed (4 to 50 kHz) Control port only modes MCLK (MHz) Sample Rate (kHz) 256x 384x 512x 768x* 8.1920 12.2880 16.3840 24.5760 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 MCLK Ratio 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 Double-Speed (50 to 100 kHz) 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 MCLK Ratio 64x 96x 128x 192x 176.4 11.2896 16.9344 22.5792 33.8688 Quad-Speed (100 to 200 kHz) 192 12.
CS4382 6. APPLICATIONS 6.1 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4382 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 5 and 6 show the recommended power arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible.
CS4382 When in Stand-Alone Mode, only the “fast” roll-off filter is available. Filter specifications can be found in Section 1, and filter response plots can be found in Figures 9 to 32. 6.6 Clock Source Selection The CS4382 has two serial clock and two left/right clock inputs. The SDINxCLK bits in the control port allow the user to set which SCLK/LRCK pair is used to latch the data for each SDINx pin.
CS4382 7.1 Enabling the Control Port On the CS4382 the control port pins are shared with stand-alone configuration pins. To enable the control port, the user must set the CPEN bit. This is done by performing a I²C or SPI write. Once the control port is enabled, these pins are dedicated to control port functionality. To prevent audible artifacts, the CPEN bit (see Section 4.1.1) should be set prior to the completion of the Stand-Alone power-up sequence, approximately 1024 LRCK cycles.
CS4382 7.4.1 Writing in SPI Figure 8 shows the operation of the control port in SPI format. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0011000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP.
CS4382 7.5.
CS4382 8. FILTER PLOTS 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1 Figure 9. Single-Speed (fast) Stopband Rejection 0.4 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 10. Single-Speed (fast) Transition Band 0.02 0 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.
CS4382 0.02 0 1 0.015 2 0.01 3 Amplitude (dB) Amplitude (dB) 0.005 4 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.02 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 15. Single-Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 16. Single-Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.4 0.5 0.6 0.7 0.
CS4382 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 21. Double-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 22. Double-Speed (slow) Transition Band 0.02 0 1 0.015 2 0.01 3 Amplitude (dB) Amplitude (dB) 0.005 4 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.02 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.
CS4382 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 27. Quad-Speed (fast) Transition Band (detail) 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 28. Quad-Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.
CS4382 9. DIAGRAMS Left Channel LRCK Right Channel SCLK SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 33. Format 0 - Left Justified up to 24-bit Data Left Channel LRCK Right Channel SCLK SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 34.
CS4382 LRCK Right Channel Left Channel SCLK SDINx 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Figure 37. Format 4 - Right Justified 20-bit Data LRCK Right Channel Left Channel SCLK SDINx 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Figure 38. Format 5 - Right Justified 18-bit Data Gain dB T1=50 µs 0dB T2 = 15 µs -10dB F1 3.183 kHz F2 Frequency 10.
CS4382 A Channel Volume Control Left Channel Audio Data Σ SDINx Right Channel Audio Data MUTE Aout Ax MUTE AoutBx Σ B Channel Volume Control Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) Figure 42.
CS4382 10.PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
CS4382 12.PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L DIM MIN INCHES NOM MAX MIN MILLIMETERS NOM MAX A A1 B D D1 E E1 e* L µ --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.
CS4382 13.ORDERING INFORMATION Product Description Package Pb-Free 114 dB, 192 kHz 848-pin CS4382 channel D/A Converter LQFP CDB4382 CS4382 Evaluation Board YES - Grade Temp Range Commercial -10°C to +70°C - - Container Order # Tray Tape and Reel - CS4382-KQZ CS4382-KQZR CDB4382 14.REVISION HISTORY Release F1 F2 Changes Removed -BQ ordering option Corrected specifications for Full Scale Differential Output Voltage Updated Table 2 on page 18 Updated Section 6.
