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CS4373A

Low-power, High-performance

∆Σ

Test DAC

Features

z Digital ∆Σ Input from CS5376A Digital Filter

z Selectable Differential Analog Outputs

• Precision output (OUT±) for electronics tests

• Buffered output (

BUF±) for sensor tests

z Multiple AC and DC Operational Modes

• Signal bandwidth: DC to 100 Hz

• Max AC amplitude: 5 V

differential

• Max DC amplitude: + 2.5 V

differential

z Selectable Attenuation for CS3301A / CS3302A

• 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64

z Outstanding Performance

• AC (OUT): -116 dB THD typical, -112 dB max

• AC (BUF): -108 dB THD typical, -90 dB max

• DC absolute accuracy: 0.4% typical, 1% max

z Low Power Consumption

• AC modes / DC modes: 40 mW / 20 mW

• Sleep mode / Power Down: 1 mW / 10 µW

z Extremely Small Footprint

• 28-pin SSOP package, 8 mm x 10 mm

z Bipolar Power Supply Configuration

• VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V

Description

The CS4373A is a high-performance, differential output

digital-to-analog converter (DAC) with programmable at-

tenuation and multiple operational modes. AC test

modes measure system dynamic performance through

THD and CMRR tests while DC test modes are for gain

calibration and pulse tests.

The CS4373A is driven by a ∆Σ digital bit stream from the

CS5376A digital filter test bit stream (TBS) generator. It

has two sets of differential analog outputs, OUT and

BUF, to simplify system design as dedicated outputs for

testing the electronics channel and for in-circuit sensor

tests. Analog output attenuation is selected by simple pin

settings and matches the gain of the

CS3301A / CS3302A differential amplifiers for full-scale

testing at all gain ranges.

The CS4373A test DAC provides self-test and precision

calibration capability for high-resolution, low-frequency

multi-channel measurement systems designed from

CS3301A / CS3302A differential amplifiers,

CS5371A / CS5372A ∆Σ modulators and the CS5376A

digital filter.

ORDERING INFORMATION

See page 34.

24-Bit ∆Σ

DAC

Attenuator

Clock

Generator

TDATA

VA+ MODE(0, 1, 2) ATT(0, 1, 2) VD

VA-

VREF+

VREF-

GND

OUT+

OUT-

BUF+

BUF-

CAP+ CAP-

MCLK

MSYNC

DEC ‘06

DS699F2

Summary of content (34 pages)

PAGE 1
CS4373A Low-power, High-performance ∆Σ Test DAC Features Description ∆Σ Input from CS5376A Digital Filter z Selectable Differential Analog Outputs The CS4373A is a high-performance, differential output digital-to-analog converter (DAC) with programmable attenuation and multiple operational modes. AC test modes measure system dynamic performance through THD and CMRR tests while DC test modes are for gain calibration and pulse tests.
PAGE 2
CS4373A TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 2. GENERAL DESCRIPTION ..................................................................................................... 16 2.1 Digital Inputs .................................................................................................................... 16 2.2 Analog Outputs .......................................................................................
PAGE 3
CS4373A LIST OF FIGURES Figure 1. Digital Input Rise and Fall Times ................................................................................... 12 Figure 2. System Timing Diagram................................................................................................. 14 Figure 3. MCLK / MSYNC Timing Detail ....................................................................................... 14 Figure 4. CS4373A Block Diagram .................................................................
PAGE 4
CS4373A 1. CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. • Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25°C. • GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half. • Device is connected as shown in Figure 6 on page 17, unless otherwise noted.
PAGE 5
CS4373A TEMPERATURE CONDITIONS Parameter Symbol Min Typ Max Unit TA -40 - +85 ºC Storage Temperature Range TSTG -65 - 150 ºC Allowable Junction Temperature TJCT - - 125 ºC Junction to Ambient Thermal Impedance (4-layer PCB) ΘJA - 65 - ºC / W Ambient Operating Temperature ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Positive Analog Negative Analog Digital Symbol Min Max Parameter VA+ VAVD -0.5 -6.8 -0.5 6.8 0.5 6.
PAGE 6
CS4373A ANALOG CHARACTERISTICS Parameter Symbol Min Typ Max Unit VREF - 2.
PAGE 7
CS4373A AC DIFFERENTIAL MODES 1, 2, 3 Parameter Symbol Min Typ Max Unit 1/1 1/2 1/4 1/8 1/16 1/32 1/64 VACFS - 5 2.5 1.25 625 312.5 156.25 78.125 - Vpp Vpp Vpp mVpp mVpp mVpp mVpp (Note 8) VACBW - - 100 Hz (Note 8, 10) VACIMP - - -20 dBfs Full-scale Accuracy (Note 3, 11) 1/1 VACABS - 0.5 - 0.2 0.2 %FS Relative Accuracy (Note 12) 1/2 1/4 1/8 1/16 1/32 1/64 VACREL - 0.2 - ± 0.1 ± 0.1 ± 0.1 - 0.1 ± 0.2 - 0.2 ± 0.3 - 0.5 ± 0.5 0.
PAGE 8
CS4373A AC DIFFERENTIAL MODES 1, 2, 3 (CONT.
PAGE 9
CS4373A DC COMMON MODE 4 Parameter Symbol Min Typ Max Unit VDCCM - (VA-)+2.
PAGE 10
CS4373A DC DIFFERENTIAL MODE 5 Parameter Symbol Min Typ Max Unit 1/1 1/2 1/4 1/8 1/16 1/32 1/64 VDCFS - 2.5 1.25 625 312.5 156.25 78.125 39.0625 - V V mV mV mV mV mV Full-scale Accuracy (Note 3, 11) 1/1 VDCABS - 1.0 - 0.4 0.2 %FS Relative Accuracy (Note 12) 1/2 1/4 1/8 1/16 1/32 1/64 VDCREL - 0.2 - ± 0.1 ± 0.1 -0.1 ± 0.4 -0.2 ± 0.9 -0.5 ± 1.7 -1.0 ± 3.6 0.2 - % % % % % % (Note 14) VDCTC - 25 - µV/°C (Note 13) VDCCM - (VA-)+2.
PAGE 11
CS4373A AC COMMON MODE 6 Parameter Symbol Min Typ Max Unit VCMFS - 2.5 1.25 625 312.5 156.25 78.125 - Vpp Vpp mVpp mVpp mVpp mVpp (Note 8) VCMBW - - 100 Hz (Note 8, 10) VCMIMP - - -20 dBfs Common Mode Match (OUT± Unloaded) (Note 17, 20) VCMCMM - -115 -105 dB Common Mode Match (BUF± Unloaded, 1 kΩ Load) (Note 16, 17, 20) VCMCMM - -95 -85 dB 1/1 VACABS - - 0.3 - %FS 1/2 1/4 1/8 1/16 1/32 VACREL - - 0.1 - 0.5 - 1.0 -2.0 -5.
PAGE 12
CS4373A DIGITAL CHARACTERISTICS Parameter Symbol Min Typ Max Unit - VD V Digital Inputs High-level Input Drive Voltage (Note 22) VIH 0.6*VD Low-level Input Drive Voltage (Note 22) VIL 0.0 - 0.
PAGE 13
CS4373A DIGITAL CHARACTERISTICS (CONT.) Parameter Symbol Min Typ Max Unit fCLK - 2.
PAGE 14
CS4373A DIGITAL CHARACTERISTICS (CONT.) SYNC MCLK (2.048 MHz) MSYNC t0 TDATA (256 kHz) Figure 2. System Timing Diagram MCLK (2.048 MHz) MSYNC tmss tmsh tmclk t0 tmsync TDATA (256 kHz) ttdata Figure 3.
PAGE 15
CS4373A POWER SUPPLY CHARACTERISTICS Parameter Symbol Min Typ Max Unit AC Mode Supply Current (MODE = 1, 2, 3, 6) Analog Power Supply Current (Note 28) IA - 8 10 mA Digital Power Supply Current (Note 28) ID - 20 - µA DC Mode Supply Current (MODE = 4) Analog Power Supply Current (Note 28) IA - 2.7 - mA Digital Power Supply Current (Note 28) ID - 20 - µA Analog Power Supply Current (Note 28) IA - 4.
PAGE 16
CS4373A VA+ MODE(0, 1, 2) ATT(0, 1, 2) VD TDATA OUT+ Attenuator OUTBUF+ 24-Bit ∆Σ DAC BUF- VREF+ VREF- MCLK Clock Generator VA- CAP+ CAP- MSYNC GND Figure 4. CS4373A Block Diagram 2. GENERAL DESCRIPTION The CS4373A is a differential output digital-toanalog converter with multiple operational modes and programmable output attenuation.
PAGE 17
CS4373A 3. SYSTEM DIAGRAMS Geophone or Hydrophone Sensor CS3301A CS3302A M U X Geophone or Hydrophone Sensor CS5371A CS5372A AMP System Telem etry ∆Σ Modulator CS3301A CS3302A M U X AMP µController or Configuration EEPROM CS5376A Digital Filter Geophone or Hydrophone Sensor CS3301A CS3302A M U X Geophone or Hydrophone Sensor CS5371A CS5372A AMP ∆Σ Modulator CS3301A CS3302A M U X Com m unication Interface AMP CS4373A Test DAC Switch Switch MUX MUX Figure 5. System Diagram VA+ 0.
PAGE 18
CS4373A POWER DOWN MCLK = OFF MODE = XXX SLEEP MODES MCLK = ON MODE = 0, 7 AC TEST MODES MCLK = ON MODE = 1, 2, 3, 6 DC TEST MODES MCLK = ON MODE = 4, 5 Figure 7. Power Mode Diagram 4. POWER MODES The CS4373A has four power modes. AC test modes and DC test modes are operational modes, while the power down and sleep modes are non-operational, standby modes. sleep mode for normal data acquisition. In sleep mode the AC and DC test circuitry is inactive and the analog outputs are high impedance. 4.
PAGE 19
CS4373A 5. OPERATIONAL MODES The CS4373A has six operational modes and two sleep modes selected by the MODE2, MODE1, and MODE0 pins. only the BUF analog output is enabled, and OUT is high impedance. OUT+ Selection MODE[2:0] Mode Description OUT- CS4373A MODE 1 0 000 Sleep mode. 1 001 AC OUT and BUF outputs. 2 010 AC OUT only, BUF high-z. 3 0 11 AC BUF only, OUT high-z. 4 100 DC common mode output. 5 101 DC differential output. 6 11 0 AC common mode output.
PAGE 20
CS4373A For the opposite case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = +1.1 V SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar calculation can be done for SIG- relative to SIG+. It’s important to note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V with respect to ground on either half.
PAGE 21
CS4373A In DC differential output mode (MODE 5) the level-shifting buffer circuitry adds low-level 32 kHz switched-capacitor noise to the DC output. This noise is out of the measurement bandwidth for systems designed with CS3301A / CS3302A amplifiers and CS5371A / CS5372A modulators, and is rejected by the CS5376A digital filter. This 32 kHz switch-capacitor noise does not affect DC system tests, though it may be visible on an oscilloscope at high gain levels. OUT+ OUT- Approx -0.
PAGE 22
CS4373A VA+ 0.1µF SWITCH CONTROL 0.1µF VA- 10nF C0G SENSOR CAP+ Analog Switches CH2 BUF CH3 BUF Route BUF as diff pair VD MCLK MSYNC CAP- CH1 BUF BUF+ TDATA CS4373A ELECTRONICS CH1,2,3,4 OUT Route OUT as diff pair OUT+ OUT- 10 Ω 2.5 V VREF Route VREF as diff pair 100µF MCLK MSYNC TBSDATA BUF- CH4 BUF VA+ VD VREF+ VREF- + VA- VA- VA- 0.1µF MODE0 MODE1 MODE2 GPIO ATT0 ATT1 ATT2 GPIO DGND GPIO GPIO GPIO GPIO CS5376A SIGNALS Figure 11. Digital Inputs 6.
PAGE 23
CS4373A surement events, thereby synchronizing analog sampling across a measurement network. The timing accuracy of the input SYNC signal from measurement node to measurement node must be +/- 1 MCLK to maximize MSYNC analog sample synchronization accuracy. The CS4373A MSYNC input is rising-edge triggered and resets the internal MCLK counter/divider to guarantee synchronous operation with other system devices.
PAGE 24
CS4373A VA+ 0.1µF SWITCH CONTROL VA10nF C0G SENSOR Analog Switches CH3 BUF CH4 BUF Route BUF as diff pair VD MCLK MSYNC CAP+ CAP- CH1 BUF CH2 BUF BUF+ TDATA ELECTRONICS CH1,2,3,4 OUT Route OUT as diff pair OUT+ OUT- 10 Ω 2.5 V VREF Route VREF as diff pair 100µF MCLK MSYNC TBSDATA BUF- CS4373A VA+ VD 0.1µF MODE0 MODE1 MODE2 GPIO GPIO GPIO ATT0 ATT1 ATT2 GPIO VREF+ VREF- + VA- VA- VA- DGND GPIO GPIO CS5376A SIGNALS 0.1µF Figure 12. Analog Outputs 7.
PAGE 25
CS4373A When enabled, attenuation is applied to both the OUT and BUF differential analog outputs. The OUT± pins connect directly into the internal attenuator resistors and so attenuation accuracy is highly sensitive to load impedance on the OUT± pins. Loading on the BUF± pins does not affect attenuator accuracy. The attenuation settings of CS4373A match the gain ranges of the CS3301A / CS3302A differential amplifiers to enable full-scale testing at all gain ranges.
PAGE 26
CS4373A To VA+ Regulator 100 µF 0.1 µF 10 Ω 2.500 V VREF To VARegulator 100 µF 0.1 µF Route VREF± as a differential pair from the 100uF RC filter capacitor + 100 µF 0.1 µF 0.1 µF 0.1 µF To VREF+ To VREF- Figure 13. Voltage Reference Circuit 8. VOLTAGE REFERENCE The CS4373A requires a 2.500 V precision voltage reference to be supplied to the VREF± pins. ogy LT1019AIS8-2.5 voltage reference yields acceptable noise levels if the output is filtered with a low-pass RC filter. 8.
PAGE 27
CS4373A 8.4 VREF Input Impedance The switched-capacitor input architecture of the VREF± inputs results in an input impedance that depends on the internal capacitor size and the clock frequency. With a 15 pF internal capacitor and a 2.048 MHz MCLK the VREF input impedance is approximately [1 / [(2.048 MHz) * (15 pF)]] = 32 kΩ. While the size of the internal capacitor is fixed, the voltage reference input impedance will vary with MCLK.
PAGE 28
CS4373A To VA+ Regulator To VD Regulator 100 uF 0.1 uF 0.1 uF VA+ 100 uF VD CS4373A VA- GND To VARegulator 100 uF 0.1 uF Figure 14. Power Supply Diagram 9. POWER SUPPLIES The CS4373A has a positive analog power supply pin (VA+), a negative analog power supply pin (VA-), a digital power supply pin (VD), and a ground pin (GND). For proper operation, power must be supplied to all power supply pins, and the ground pin must be connected to system ground.
PAGE 29
CS4373A rejected as specified in Power Supply Characteristics table. the 9.4 SCR Latch-up The VA- pin is tied to the CS4373A CMOS substrate and must always be the most-negative voltage applied to the device to ensure SCR latch-up does not occur. In general, latch-up may occur when any pin voltage exceeds the limits of the Absolute Maximum Ratings table. It is recommended to connect the VA- power supply to system ground (GND) with a reverse-biased Schottky diode.
PAGE 30
CS4373A 10. TERMINOLOGY Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated rms noise from DC to 430 Hz. The following formula is used to calculate SNR: SNR = 20log Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all harmonic frequencies from DC to 430 Hz.
PAGE 31
CS4373A 11.
PAGE 32
CS4373A Pin Name ATT2, ATT1, ATT0 MODE2, MODE1, MODE0 GND 32 Pin # I/O 22, 23, 24 25, 26, 27 28 I Pin Description Attenuation Range. Selects the output attenuation range. Attenuation I Selection ATT[2:0] Attenuation dB 0 000 1/1 0 dB 1 001 1/2 -6.02 dB 2 010 1/4 -12.04 dB 3 0 11 1/8 -18.06 dB 4 100 1/16 -24.08 dB 5 101 1/32 -30.10 dB 6 11 0 1/64 -36.12 dB 7 111 reserved reserved Mode Selection. Determines the operational mode of the device.
PAGE 33
CS4373A 12. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 E e b2 SIDE VIEW A ∝ A1 L END VIEW SEATING PLANE 1 2 3 TOP VIEW DIM A A1 A2 b D E E1 e L ∝ MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0° INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4° MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8° MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0° MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4° NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.
PAGE 34
CS4373A 13.ORDERING INFORMATION Model CS4373A-ISZ (lead free) Temperature Package -40 to +85 °C 28-pin SSOP 14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life 260 °C 3 7 Days CS4373A-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 15.REVISION HISTORY Revision Date PP1 MAR 2003 Preliminary release for CS4373.