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114 dB, 192 kHz 6-Channel D/A Converter

Features

 Advanced Multi-bit Delta Sigma Architecture

 24-bit Conversion

 Automatic Detection of Sample Rates up to

192 kHz

 114 dB Dynamic Range

 -100 dB THD+N

 Direct Stream Digital Mode

– Non-Decimating Volume Control

– On-Chip 50 kHz Filter

– Matched PCM and DSD Analog Output

Levels

 Selectable Digital Filters

 Volume Control with 1/2-dB Step Size and Soft

Ramp

 Low Clock-Jitter Sensitivity

 +5 V Analog Supply, +2.5 V Digital Supply

 Separate 1.8 to 5 V Logic Supplies for the

Control and Serial Ports

Description

The CS4365 is a complete 6-channel digital-to-analog

system. This D/A system includes digital de-emphasis,

half-dB step size volume control, ATAPI channel mix-

ing, selectable fast and slow digital interpolation filters

followed by an oversampled, multi-bit delta sigma mod-

ulator which includes mismatch-shaping technology

that eliminates distortion due to capacitor mismatch.

Following this stage is a multi-element switched capac-

itor stage and low-pass filter with differential analog

outputs.

The CS4365 also has a proprietary DSD processor

which allows for volume control and 50 kHz on-chip fil-

tering without an intermediate decimation stage. It also

offers an optional path for direct DSD conversion by di-

rectly using the multi-element switched capacitor array.

The CS4365 is available in a 48-pin LQFP package in

both Commercial (-40°C to +85°C) and Automotive

(-40°C to +105°C) grades. The CDB4365 Customer

Demonstration board is also available for device evalu-

ation and implementation suggestions. Please see

“Ordering Information” on page 51 for complete details.

The CS4365 accepts PCM data at sample rates from

4 kHz to 216 kHz, DSD audio data, and delivers excel-

lent sound quality. These features are ideal for multi-

channel audio systems, including SACD players, A/V

receivers, digital TV’s, mixing consoles, effects proces-

sors, sound cards, and automotive audio systems.

Control Port Supply = 1.8 V to 5 V

Configuration

Internal Voltage

Reference

Reset

Serial Interface

Level Translator

Digital Supply = 2.5 V

Hardware Mode or

C/SPI Software Mode

Control Data

Analog Supply = 5 V

Six Channels of

Differential

Outputs

PCM Serial

Audio Input

Volume

Controls

Digital

Filters

Switch-Cap

DAC and

Analog Filters

Multi-bit ΔΣ

Modulators

DSD Audio

Input

DSD Processor

-Volume control

-50 kHz filter

External Mute

Control

Mute Signals

Serial Audio Port

Supply = 1.8 V to 5 V

FEB '08

DS670F2

CS4365

Summary of content (52 pages)

PAGE 1
CS4365 114 dB, 192 kHz 6-Channel D/A Converter Features Description Advanced Multi-bit Delta Sigma Architecture The CS4365 is a complete 6-channel digital-to-analog system. This D/A system includes digital de-emphasis, half-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma modulator which includes mismatch-shaping technology that eliminates distortion due to capacitor mismatch.
PAGE 2
CS4365 TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................ 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ................................................................
PAGE 3
CS4365 6.2.3 PCM/DSD Selection (DSD/PCM) .......................................................................................... 35 6.2.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 35 6.2.5 Power Down (PDN) ............................................................................................................... 35 6.3 PCM Control (address 03h) .............................................................................
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CS4365 LIST OF FIGURES Figure 1.Serial Audio Interface Timing ...................................................................................................... 15 Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16 Figure 3.Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode ........................... 16 Figure 4.Control Port Timing - I²C Format ...................................................
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CS4365 LIST OF TABLES Table 1. Single-Speed Mode Standard Frequencies ................................................................................ 21 Table 2. Double-Speed Mode Standard Frequencies ............................................................................... 21 Table 3. Quad-Speed Mode Standard Frequencies ................................................................................. 21 Table 4. PCM Digital Interface Format, Hardware Mode Options ...................................
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CS4365 AOUTB1- AOUTB1+ AOUTA1+ AOUTA1- DSD_SCLK MUTEC1 TST VLS DSDB3 TST DSDA3 DSDB2 1.
PAGE 7
CS4365 Pin Name # Pin Description VQ 21 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance.
PAGE 8
CS4365 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters Symbol Min Typ Max Units Analog power Digital internal power Serial data port interface power Control port interface power Ambient Operating Temperature (Power Applied) Commercial Grade (-CQZ) Automotive Grade (-DQZ) VA VD VLS VLC 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.
PAGE 9
CS4365 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-scale 997 Hz input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
PAGE 10
CS4365 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V; VD = 2.37 to 2.63 V; TA = -40°C to 85°C; Full-scale 997 Hz input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
PAGE 11
CS4365 POWER AND THERMAL CHARACTERISTICS Parameters Symbol Min Typ Max Units normal operation, VA= 5 V VD= 2.5 V (Note 5) Interface current, VLC=5 V VLS=5 V (Note 6) power-down state (all supplies) Power Dissipation (Note 4) VA = 5 V, VD = 2.
PAGE 12
CS4365 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. See Note 12. Fast Roll-Off Parameter Unit Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response to -0.
PAGE 13
CS4365 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) Slow Roll-Off (Note 8) Parameter Unit Min Typ Max 0 0 - 0.417 0.499 Fs Fs -0.01 - +0.01 dB .583 - - Fs 64 - - dB Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 10) Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) - 7.8/Fs - s Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - ±0.36 ±0.21 ±0.
PAGE 14
CS4365 DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-Level Input Voltage Min Typ Max Units Iin 8 - ±10 0.30•VLS 0.30•VLC 0.20•VLC μA pF V V V V V Serial I/O Control I/O Serial I/O Control I/O Control I/O = 3.3 V, 5 V VIH VIH VIL VIL VOL 0.70•VLS 0.70•VLC - Low-Level Output Voltage (IOL = -1.2 mA) Control I/O = 1.8 V, 2.5 V VOL - - 0.
PAGE 15
CS4365 SWITCHING CHARACTERISTICS - PCM Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF. Parameters Symbol RST pin Low Pulse Width (Note 14) MCLK Frequency MCLK Duty Cycle (Note 15) Min Max Units 1 - ms 1.024 55.
PAGE 16
CS4365 SWITCHING CHARACTERISTICS - DSD Logic 0 = GND; Logic 1 = VLS; CL = 20 pF. Parameter Symbol MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency tsclkl tsclkh (64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation Mode) tsdlrs tsdh tdpm Min Typ Max Unit 40 160 160 1.024 2.048 20 20 -20 - 60 3.2 6.
PAGE 17
CS4365 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF. Symbol Min Max Unit SCL Clock Frequency Parameter fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.
PAGE 18
CS4365 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF. Symbol Min Max Unit CCLK Clock Frequency Parameter fsclk - 6 MHz RST Rising Edge to CS Falling tsrs 500 - ns tspi 500 - ns CS High Time Between Transmissions tcsh 1.
PAGE 19
CS4365 3. TYPICAL CONNECTION DIAGRAM +2.5 V +5 V 1 µF + + 0.1 µF 0.1 µF 4 VD 1 µF 32 VA 220 Ω 6 7 PCM Digital Audio Source 9 8 11 13 MCLK AOUTA1+ LRCK AOUTA1- SCLK SDIN1 AOUTB1+ SDIN2 AOUTB1AOUTA2+ +1.8 V to +5 V AOUTA2- VLS CS4365 0.
PAGE 20
CS4365 +5 V +2.5 V 1 µF + 0.1 µF 0.1 µF 4 VD 220 Ω 6 7 PCM Digital Audio Source 9 8 11 13 MCLK AOUTA1+ LRCK AOUTA1- SCLK MUTEC1 SDIN1 SDIN3 AOUTB1+ MUTEC2 VLS AOUTA2+ AOUTA2- 3 2 1 DSD Audio Source 48 47 46 42 DSDA1 MUTEC3 AOUTB2+ DSDB2 AOUTB2- DSDA3 DSD_SCLK MUTEC4 AOUTA3+ +1.
PAGE 21
CS4365 4. APPLICATIONS The CS4365 serially accepts two’s complement formatted PCM data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
PAGE 22
CS4365 4.2 Mode Select In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continually scanned for any changes; however, the mode should only be changed while the device is in reset (RST pin low) to ensure proper switching from one mode to another. These pins require connection to supply or ground as outlined in Figure 7. For M0, M1, and M2, supply is VLC. For M3 and M4, supply is VLS. Tables 4 - 6 show the decode of these pins.
PAGE 23
CS4365 4.3 Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, and One-Line Mode (OLM) digital interface formats with varying bit depths from 16 to 32, as shown in Figures 8-15. Data is clocked into the DAC on the rising edge. OLM configuration is only supported in Software Mode. Left Channel LRCK Right Channel SCLK SDINx MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB Figure 8.
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CS4365 LRCK Right Channel Left Channel SCLK SDINx 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 clocks Figure 13. Format 5 - Right-Justified 18-bit Data 4.3.1 OLM #1 OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1.
PAGE 25
CS4365 4.5 Interpolation Filter To accommodate the increasingly complex requirements of digital audio systems, the CS4365 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Filter Plots” on page 45 for more details).
PAGE 26
CS4365 4.7 ATAPI Specification The CS4365 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 9 on page 42 and Figure 17 for additional information. A Channel Volume Control Left Channel Audio Data Σ SDINx Right Channel Audio Data MUTE Aout Ax MUTE AoutBx Σ B Channel Volume Control Figure 17. ATAPI Block Diagram (x = channel pair 1, 2, or 3) 4.
PAGE 27
CS4365 DSD Phase Modulation Mode DSD Normal Mode BCKA (64Fs) Not Used DSD_SCLK BCKA (128Fs) DSD_SCLK DSD_SCLK BCKD (64Fs) Not Used DSDAx, DSDBx D0 D0 D1 D1 D1 D2 D2 DSDAx, DSDBx Not Used Figure 18. DSD Phase Modulation Mode Diagram 4.9 Grounding and Power Supply Arrangements As with any high-resolution converter, the CS4365 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized.
PAGE 28
CS4365 4.10 Analog Output and Filtering The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on the CS4365 evaluation board, CDB4365, as seen in Figure 20. The CS4365 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
PAGE 29
CS4365 4.11 The MUTEC Outputs The MUTEC1-6 pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4365 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active.
PAGE 30
CS4365 4.12.2 Software Mode 1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2. 2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode). 3.
PAGE 31
CS4365 4.14.2.1 I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section . 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.
PAGE 32
CS4365 4.14.3 SPI Mode In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 23 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a high to low transition on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK. 4.14.3.
PAGE 33
CS4365 5. REGISTER QUICK REFERENCE Addr Function 01h Chip Revision 02h Mode Control default default 03h PCM Control default 04h DSD Control 05h Filter Control 06h Invert Control 07h Group Control 08h Ramp and Mute 09h Mute Control default default default default default default 0Ah Mixing Control Pair 1 (AOUTx1) default 0Bh Vol. Control A1 default 0Ch Vol. Control B1 default 0Dh Mixing Control Pair 2 (AOUTx1) default 0Eh Vol. Control A2 default 0Fh Vol.
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CS4365 6. REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Chip Revision (address 01h) 7 6 5 4 3 2 1 0 PART4 0 PART3 1 PART2 1 PART1 0 PART0 1 REV2 - REV1 - REV0 - 6.1.1 Part Number ID (PART) [Read Only] 01101- CS4365 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.
PAGE 35
CS4365 6.2.3 PCM/DSD Selection (DSD/PCM) Default = 0 0 - PCM 1 - DSD Function: This function selects DSD or PCM Mode. The appropriate data and clocks should be present before changing modes, or else MUTE should be selected. 6.2.4 DAC Pair Disable (DACx_DIS) Default = 0 0 - DAC Pair x Enabled 1 - DAC Pair x Disabled Function: When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
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CS4365 DIF3 DIF2 DIF1 DIF0 0 0 0 0 0 0 1 1 X 0 0 0 0 1 1 0 0 X 0 0 1 1 0 0 0 0 X 0 1 0 1 0 1 0 1 X DESCRIPTION FORMAT Left-Justified, up to 24-bit data I²S, up to 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data One-Line Mode 1, 24-bit Data One-Line Mode 2, 20-bit Data All other combinations are Reserved 0 1 2 3 4 5 8 9 Table 7. Digital Interface Formats - PCM Mode 6.3.
PAGE 37
CS4365 6.4.2 Direct DSD Conversion (DIR_DSD) Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions. When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
PAGE 38
CS4365 6.5 Filter Control (address 05h) 7 6 5 4 3 2 1 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 FILT_SEL 0 6.5.1 Interpolation Filter Select (FILT_SEL) Function: When set to 0 (default), the Interpolation Filter has a fast roll-off. When set to 1, the Interpolation Filter has a slow roll-off. The specifications for each filter can be found in the Analog characteristics table, and response plots can be found in Figures 24 to 47. 6.
PAGE 39
CS4365 6.7.2 Channel A Volume = Channel B Volume (Px_A=B) Default = 0 0 - Disabled 1 - Enabled Function: The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled. 6.7.
PAGE 40
CS4365 Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 6.8.
PAGE 41
CS4365 6.8.5 DSD Auto-Mute (DAMUTE) Function: When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification). A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. 6.8.
PAGE 42
CS4365 6.10 Mixing Control (address 0Ah, 0Dh, 10h, 13h) 7 6 5 4 3 2 1 0 Reserved 0 Px_DEM1 0 Px_DEM0 0 PxATAPI4 0 PxATAPI3 1 PxATAPI2 0 PxATAPI1 0 PxATAPI0 1 6.10.1 De-Emphasis Control (PX_DEM1:0) Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 μs/50 μs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 16) De-emphasis is only available in Single-Speed Mode. 6.10.
PAGE 43
CS4365 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx 1 0 0 1 1 MUTE [(bL+aR)/2] 1 0 1 0 0 aR MUTE 1 0 1 0 1 aR bR 1 0 1 1 0 aR bL 1 0 1 1 1 aR [(aL+bR)/2] 1 1 0 0 0 aL MUTE 1 1 0 0 1 aL bR 1 1 0 1 0 aL bL 1 1 0 1 1 aL [(aL+bR)/2] 1 1 1 0 0 [(aL+bR)/2] MUTE 1 1 1 0 1 [(aL+bR)/2] bR 1 1 1 1 0 [(bL+aR)/2] bL 1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2] Table 9. ATAPI Decode Table 6.
PAGE 44
CS4365 6.12 PCM Clock Mode (address 16h) 7 6 5 4 3 2 1 0 Reserved 0 Reserved 0 MCLKDIV 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV) Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged.
PAGE 45
CS4365 0 0 −20 −20 −40 −40 Amplitude (dB) Amplitude (dB) 7. FILTER PLOTS −60 −60 −80 −80 −100 −100 −120 0.4 −120 0.4 1 0.9 0.8 0.7 0.6 Frequency(normalized to Fs) 0.5 Figure 24. Single-Speed (fast) Stopband Rejection 0.42 0.44 0.46 0.48 0.5 0.52 Frequency(normalized to Fs) 0.54 0.56 0.58 0.6 Figure 25. Single-Speed (fast) Transition Band 0 0.02 −1 0.015 −2 0.01 0.005 −4 Amplitude (dB) Amplitude (dB) −3 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.
PAGE 46
CS4365 0.02 0 −1 0.015 −2 0.01 −3 Amplitude (dB) Amplitude (dB) 0.005 −4 −5 −6 0 −0.005 −7 −0.01 −8 −0.015 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 −0.02 0.55 Figure 30. Single-Speed (slow) Transition Band (detail) 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 0.5 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0.05 Figure 31. Single-Speed (slow) Passband Ripple 0 60 60 80 80 100 100 120 0 120 0.
PAGE 47
CS4365 0 20 20 40 40 Amplitude (dB) Amplitude (dB) 0 60 60 80 80 100 100 120 120 0.2 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.8 0.9 1 Figure 36. Double-Speed (slow) Stopband Rejection 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 Figure 37. Double-Speed (slow) Transition Band 0 0.02 1 0.015 2 0.01 0.005 4 Amplitude (dB) Amplitude (dB) 3 5 6 0 0.005 7 0.01 8 0.015 9 10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.
PAGE 48
CS4365 0.2 0 1 0.15 2 0.1 3 Amplitude (dB) Amplitude (dB) 0.05 4 5 6 0 0.05 7 0.1 8 0.15 9 10 0.45 0.2 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55 Figure 42. Quad-Speed (fast) Transition Band (detail) 0 0.05 0.1 0.15 Frequency(normalized to Fs) 0.2 0.25 Figure 43. Quad-Speed (fast) Passband Ripple 0 0 20 40 40 Amplitude (dB) Amplitude (dB) 20 60 60 80 80 100 100 120 120 0.1 0.2 0.3 0.4 0.5 0.6 0.
PAGE 49
CS4365 8. PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth.
PAGE 50
CS4365 9. PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING E E1 D D1 1 e B ∝ A A1 L DIM MIN INCHES NOM MAX MIN MILLIMETERS NOM MAX A A1 B D D1 E E1 e* L µ --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000° 0.055 0.004 0.009 0.354 0.28 0.354 0.28 0.020 0.24 4° 0.063 0.006 0.011 0.366 0.280 0.366 0.280 0.024 0.030 7.000° --0.05 0.17 8.70 6.90 8.70 6.90 0.40 0.45 0.00° 1.40 0.10 0.22 9.0 BSC 7.0 BSC 9.0 BSC 7.0 BSC 0.50 BSC 0.60 4° 1.60 0.15 0.27 9.30 7.10 9.30 7.10 0.60 0.75 7.
PAGE 51
CS4365 10.ORDERING INFORMATION Product Description CS4365 114 dB, 192 kHz 6-channel D/A Converter CDB4365 CS4365 Evaluation Board Package Pb-Free 48-pin LQFP YES - Grade Temp Range Container Tray Commercial -40°C to +85°C Tape & Reel Tray Automotive -40°C to +105°C Tape & Reel - Order # CS4365-CQZ CS4365-CQZR CS4365-DQZ CS4365-DQZR CDB4365 11.REFERENCES 1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris.
PAGE 52
CS4365 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied).