User Manual
CS4360
DS517F2 23
4.3.2 Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.
4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for F
s
equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs.
Notes: De-emphasis is only available in Single-speed Mode.
LRCK
SCLK
Left Channel
Right Channel
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1 -2 -3 -4
LSB
MSB
LS B
Figure 15. Left Justified up to 24-Bit Data
LRCK
SCLK
Left Channel
Right Channel
SDIN +3 +2 +1+5 +4
MSB
-1 -2 -3 -4 -5
+3 +2 +1+5 +4
-1 -2 -3 -4
MSB
LSB LSB
Figure 16. I
2
S, up to 24-Bit Data
LRCK
SCLK
Left Channel
SDIN
+6 +5 +4 +3 +2+1+7-1 -2 -3 -4 -5LSB
Right Channel
MSB LSB
+6 +5 +4 +3 +2+1+7-1 -2 -3 -4 -5
MSB LSB
Figure 17. Right Justified Data
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 18. De-emphasis Curve