Owner manual

8 DS895F2
CS4354
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample Rate Range/Operational
Mode Detect” on page 13 for supported ratios and frequencies. SSM = Single-Speed Mode,
DSM = Double-Speed Mode, QSM = Quad-Speed Mode.
13. SCLK period is defined by the SCLK / LRCK ratio. The SCLK/LRCK ratio may be either 32, 48, or 64.
See Table 5 on page 14.
14.
Parameters Symbol Min Typ Max Units
MCLK frequency 7.6 - 55.3 MHz
MCLK duty cycle 35 - 65 %
Input sample rate All MCLK/LRCK ratios combined
(Note 12) (SSM) 256x, 384x, 512x, 768x, 1024x
(DSM) 128x, 192x, 256x, 384x, 512x
(QSM) 128x, 192x, 256x
Fs 30
30
84
170
-
-
-
-
216
54
108
216
kHz
kHz
kHz
kHz
External SCLK Mode
LRCK duty cycle 45 - 55 %
SCLK pulse width low t
sclkl
20 - - ns
SCLK pulse width high t
sclkh
20 - - ns
SCLK duty cycle 45 - 55 %
SCLK rising to LRCK edge delay t
slrd
20 - - ns
LRCK edge to SCLK rising delay t
slrs
20 - - ns
SDIN valid to SCLK rising setup time t
sdlrs
20 - - ns
SCLK rising to SDIN hold time t
sdh
20 - - ns
Internal SCLK Mode
LRCK duty cycle
--
SCLK period (Note 13) t
sclkw
--ns
MCLK falling to LRCK edge t
mclkf
-ns
LRCK edge to SCLK rising t
sclkr
- (Note 14) -ns
SDIN valid to SCLK rising setup time t
sdlrs
--ns
SCLK rising to SDIN hold time
MCLK / LRCK = 1024, 512, 256, 128
t
sdh
--
ns
MCLK / LRCK = 768, 384, 192 - -
50%
1
2MCLK

----------------------------
–
50%
1
2MCLK

----------------------------+
10
9
SCLK
----------------
10
9
–
4MCLK
---------------------------
10
9
4MCLK
---------------------------
10
9
512 Fs
----------------------- 10+
10
9
512 Fs
----------------------- 15+
10
9
384 Fs
----------------------- 15+
t
sclkr
t
sclkw
2
-----------------
10
9
2MCLK

---------------------------t
mclkf
++=